return (readl_gicc(GICC_IAR) & GICC_IA_IRQ);
}
-static void gicv2_set_irq_type(struct irq_desc *desc)
+static void gicv2_set_irq_type(struct irq_desc *desc, unsigned int type)
{
uint32_t cfg, actual, edgebit;
unsigned int irq = desc->irq;
- unsigned int type = desc->arch.type;
spin_lock(&gicv2.lock);
/* Set edge / level */
MPIDR_AFFINITY_LEVEL(mpidr, 0));
}
-static void gicv3_set_irq_type(struct irq_desc *desc)
+static void gicv3_set_irq_type(struct irq_desc *desc, unsigned int type)
{
uint32_t cfg, actual, edgebit;
void __iomem *base;
unsigned int irq = desc->irq;
- unsigned int type = desc->arch.type;
/* SGI's are always edge-triggered not need to call GICD_ICFGR0 */
ASSERT(irq >= NR_GIC_SGI);
gic_restore_pending_irqs(v);
}
-static void gic_set_irq_type(struct irq_desc *desc)
+static void gic_set_irq_type(struct irq_desc *desc, unsigned int type)
{
ASSERT(spin_is_locked(&desc->lock));
- ASSERT(desc->arch.type != IRQ_TYPE_INVALID);
+ ASSERT(type != IRQ_TYPE_INVALID);
- gic_hw_ops->set_irq_type(desc);
+ gic_hw_ops->set_irq_type(desc, type);
}
static void gic_set_irq_priority(struct irq_desc *desc, unsigned int priority)
desc->handler = gic_hw_ops->gic_host_irq_type;
- gic_set_irq_type(desc);
+ gic_set_irq_type(desc, desc->arch.type);
gic_set_irq_priority(desc, priority);
}
desc->handler = gic_hw_ops->gic_guest_irq_type;
set_bit(_IRQ_GUEST, &desc->status);
- gic_set_irq_type(desc);
+ gic_set_irq_type(desc, desc->arch.type);
gic_set_irq_priority(desc, priority);
p->desc = desc;
void (*deactivate_irq)(struct irq_desc *irqd);
/* Read IRQ id and Ack */
unsigned int (*read_irq)(void);
- /* Set IRQ type - type is taken from desc->arch.type */
- void (*set_irq_type)(struct irq_desc *desc);
+ /* Set IRQ type */
+ void (*set_irq_type)(struct irq_desc *desc, unsigned int type);
/* Set IRQ priority */
void (*set_irq_priority)(struct irq_desc *desc, unsigned int priority);
/* Send SGI */