]> xenbits.xensource.com Git - xen.git/commitdiff
x86/smpboot.c: use plain bool
authorWei Liu <wei.liu2@citrix.com>
Fri, 30 Jun 2017 16:29:15 +0000 (17:29 +0100)
committerWei Liu <wei.liu2@citrix.com>
Tue, 4 Jul 2017 13:54:42 +0000 (14:54 +0100)
Signed-off-by: Wei Liu <wei.liu2@citrix.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
xen/arch/x86/smpboot.c
xen/arch/x86/time.c
xen/include/asm-x86/time.h

index f375eb682de86f347b8ee08680d3228371c30f8e..8d91f6ca01e40039b0bd418409fc20706556426f 100644 (file)
@@ -106,7 +106,7 @@ static void smp_store_cpu_info(int id)
  * TSC's upper 32 bits can't be written in earlier CPUs (before
  * Prescott), there is no way to resync one AP against BP.
  */
-bool_t disable_tsc_sync;
+bool disable_tsc_sync;
 
 static atomic_t tsc_count;
 static uint64_t tsc_value;
@@ -975,7 +975,8 @@ int cpu_add(uint32_t apic_id, uint32_t acpi_id, uint32_t pxm)
     /* Physically added CPUs do not have synchronised TSC. */
     if ( boot_cpu_has(X86_FEATURE_TSC_RELIABLE) )
     {
-        static bool_t once_only;
+        static bool once_only;
+
         if ( !test_and_set_bool(once_only) )
             printk(XENLOG_WARNING
                    " ** New physical CPU %u may have skewed TSC and hence "
index 780baa55a3c730d0722917f3f923ea0733290af4..b988b94d2e356f65d75d88a87f02585185750d1e 100644 (file)
@@ -1568,7 +1568,7 @@ static void __init tsc_check_writability(void)
         cpuidle_disable_deep_cstate();
 
     /* synchronize_tsc_slave() must do nothing */
-    disable_tsc_sync = 1;
+    disable_tsc_sync = true;
 }
 
 static void __init reset_percpu_time(void *unused)
index ef989a69b33d735f525ee9ffc7085f8595490f69..046302ef199fb430c0f2a042a28d1ef1eebdbf1f 100644 (file)
@@ -24,7 +24,7 @@
 
 typedef u64 cycles_t;
 
-extern bool_t disable_tsc_sync;
+extern bool disable_tsc_sync;
 
 static inline cycles_t get_cycles(void)
 {