this_cpu(tlbflush_time) = t;
}
-void write_cr3(unsigned long cr3)
+void switch_cr3(unsigned long cr3)
{
unsigned long flags, cr4;
u32 t;
cr4 = read_cr4();
write_cr4(cr4 & ~X86_CR4_PGE);
- asm volatile ( "mov %0, %%cr3" : : "r" (cr3) : "memory" );
+ write_cr3(cr3);
write_cr4(cr4);
post_flush(t);
void write_ptbase(struct vcpu *v)
{
get_cpu_info()->root_pgt_changed = 1;
- write_cr3(v->arch.cr3);
+ switch_cr3(v->arch.cr3);
}
/*
get_cpu_info()->root_pgt_changed = 1;
/* Don't flush user global mappings from the TLB. Don't tick TLB clock. */
- asm volatile ( "mov %0, %%cr3" : : "r" (v->arch.cr3) : "memory" );
+ write_cr3(v->arch.cr3);
if ( !(v->arch.flags & TF_kernel_mode) )
return;
asm volatile ( "lgdt %0" : : "m" (gdt_desc) );
}
- write_cr3(virt_to_maddr(efi_l4_pgtable));
+ switch_cr3(virt_to_maddr(efi_l4_pgtable));
return state;
}
{
if ( !state->cr3 )
return;
- write_cr3(state->cr3);
+ switch_cr3(state->cr3);
if ( is_pv_vcpu(current) && !is_idle_vcpu(current) )
{
struct desc_ptr gdt_desc = {
}
/* Write pagetable base and implicitly tick the tlbflush clock. */
-void write_cr3(unsigned long cr3);
+void switch_cr3(unsigned long cr3);
/* flush_* flag fields: */
/*
return cr2;
}
+static inline void write_cr3(unsigned long val)
+{
+ asm volatile ( "mov %0, %%cr3" : : "r" (val) : "memory" );
+}
+
static inline unsigned long read_cr4(void)
{
return get_cpu_info()->cr4;