#include <locale.h>
#include <xenctrl.h>
+#include <xenevtchn.h>
+#include <xenforeignmemory.h>
+#include <xendevicemodel.h>
#include <xen/hvm/ioreq.h>
#include "debug.h"
typedef enum {
DEMU_SEQ_UNINITIALIZED = 0,
- DEMU_SEQ_INTERFACE_OPEN,
+ DEMU_SEQ_XENCTRL_OPEN,
+ DEMU_SEQ_XENEVTCHN_OPEN,
+ DEMU_SEQ_XENFOREIGNMEMORY_OPEN,
+ DEMU_SEQ_XENDEVICEMODEL_OPEN,
DEMU_SEQ_SERVER_REGISTERED,
DEMU_SEQ_SHARED_IOPAGE_MAPPED,
DEMU_SEQ_BUFFERED_IOPAGE_MAPPED,
DEMU_SEQ_SERVER_ENABLED,
DEMU_SEQ_PORT_ARRAY_ALLOCATED,
- DEMU_SEQ_EVTCHN_OPEN,
DEMU_SEQ_PORTS_BOUND,
DEMU_SEQ_BUF_PORT_BOUND,
DEMU_SEQ_DEVICE_INITIALIZED,
} demu_seq_t;
typedef struct demu_state {
- demu_seq_t seq;
- xc_interface *xch;
- xc_evtchn *xceh;
- domid_t domid;
- unsigned int vcpus;
- ioservid_t ioservid;
- shared_iopage_t *iopage;
- evtchn_port_t *ioreq_local_port;
- buffered_iopage_t *buffered_iopage;
- evtchn_port_t buf_ioreq_port;
- evtchn_port_t buf_ioreq_local_port;
+ demu_seq_t seq;
+ xc_interface *xch;
+ xenevtchn_handle *xeh;
+ xenforeignmemory_handle *xfh;
+ xendevicemodel_handle *xdh;
+ domid_t domid;
+ unsigned int vcpus;
+ ioservid_t ioservid;
+ shared_iopage_t *iopage;
+ evtchn_port_t *ioreq_local_port;
+ buffered_iopage_t *buffered_iopage;
+ evtchn_port_t buf_ioreq_port;
+ evtchn_port_t buf_ioreq_local_port;
} demu_state_t;
static demu_state_t demu_state;
{
if (ioreq->dir == IOREQ_READ) {
if (!ioreq->data_is_ptr) {
- ioreq->data = (uint64_t)pci_bar_read(0, ioreq->addr, ioreq->size);
+ ioreq->data = (uint64_t)pci_bar_read(0, ioreq->addr,
+ ioreq->size);
} else {
assert(FALSE);
}
} else if (ioreq->dir == IOREQ_WRITE) {
if (!ioreq->data_is_ptr) {
- pci_bar_write(0, ioreq->addr, ioreq->size, (uint32_t)ioreq->data);
+ pci_bar_write(0, ioreq->addr, ioreq->size,
+ (uint32_t)ioreq->data);
} else {
assert(FALSE);
}
{
if (ioreq->dir == IOREQ_READ) {
if (!ioreq->data_is_ptr) {
- ioreq->data = (uint64_t)pci_bar_read(1, ioreq->addr, ioreq->size);
+ ioreq->data = (uint64_t)pci_bar_read(1, ioreq->addr,
+ ioreq->size);
} else {
assert(FALSE);
}
} else if (ioreq->dir == IOREQ_WRITE) {
if (!ioreq->data_is_ptr) {
- pci_bar_write(1, ioreq->addr, ioreq->size, (uint32_t)ioreq->data);
+ pci_bar_write(1, ioreq->addr, ioreq->size,
+ (uint32_t)ioreq->data);
} else {
assert(FALSE);
}
{
if (ioreq->dir == IOREQ_READ) {
if (!ioreq->data_is_ptr) {
- ioreq->data = (uint32_t)pci_config_read(ioreq->addr, ioreq->size);
+ ioreq->data = (uint32_t)pci_config_read(ioreq->addr,
+ ioreq->size);
} else {
assert(FALSE);
}
} else if (ioreq->dir == IOREQ_WRITE) {
if (!ioreq->data_is_ptr) {
- pci_config_write(ioreq->addr, ioreq->size, (uint32_t)ioreq->data);
+ pci_config_write(ioreq->addr, ioreq->size,
+ (uint32_t)ioreq->data);
} else {
assert(FALSE);
}
assert(demu_state.seq < DEMU_SEQ_INITIALIZED);
switch (++demu_state.seq) {
- case DEMU_SEQ_INTERFACE_OPEN:
- DBG(">INTERFACE_OPEN\n");
+ case DEMU_SEQ_XENCTRL_OPEN:
+ DBG(">XENCTRL_OPEN\n");
+ break;
+
+ case DEMU_SEQ_XENEVTCHN_OPEN:
+ DBG(">XENEVTCHN_OPEN\n");
+ break;
+
+ case DEMU_SEQ_XENFOREIGNMEMORY_OPEN:
+ DBG(">XENFOREIGNMEMORY_OPEN\n");
+ break;
+
+ case DEMU_SEQ_XENDEVICEMODEL_OPEN:
+ DBG(">XENDEVICEMODEL_OPEN\n");
break;
case DEMU_SEQ_SERVER_REGISTERED:
DBG(">PORT_ARRAY_ALLOCATED\n");
break;
- case DEMU_SEQ_EVTCHN_OPEN:
- DBG(">EVTCHN_OPEN\n");
- break;
-
case DEMU_SEQ_PORTS_BOUND: {
int i;
DBG("<DEVICE_INITIALIZED\n");
device_teardown();
- demu_state.seq = DEMU_SEQ_PORTS_BOUND;
+ demu_state.seq = DEMU_SEQ_BUF_PORT_BOUND;
}
- if (demu_state.seq >= DEMU_SEQ_PORTS_BOUND) {
+ if (demu_state.seq >= DEMU_SEQ_BUF_PORT_BOUND) {
DBG("<EVTCHN_BUF_PORT_BOUND\n");
- evtchn_port_t port;
+ evtchn_port_t port;
port = demu_state.buf_ioreq_local_port;
DBG("%u\n", port);
- (void) xc_evtchn_unbind(demu_state.xceh, port);
+ (void) xenevtchn_unbind(demu_state.xeh, port);
demu_state.seq = DEMU_SEQ_PORTS_BOUND;
}
if (demu_state.seq >= DEMU_SEQ_PORTS_BOUND) {
DBG("<EVTCHN_PORTS_BOUND\n");
- demu_state.seq = DEMU_SEQ_EVTCHN_OPEN;
+ demu_state.seq = DEMU_SEQ_PORT_ARRAY_ALLOCATED;
}
- if (demu_state.seq >= DEMU_SEQ_EVTCHN_OPEN) {
- int i;
+ if (demu_state.seq >= DEMU_SEQ_PORT_ARRAY_ALLOCATED) {
+ unsigned int i;
- DBG("<EVTCHN_OPEN\n");
+ DBG("<PORT_ARRAY_ALLOCATED\n");
for (i = 0; i < demu_state.vcpus; i++) {
- evtchn_port_t port;
+ evtchn_port_t port;
port = demu_state.ioreq_local_port[i];
if (port >= 0) {
DBG("VCPU%d: %u\n", i, port);
- (void) xc_evtchn_unbind(demu_state.xceh, port);
+ (void) xenevtchn_unbind(demu_state.xeh, port);
}
}
- xc_evtchn_close(demu_state.xceh);
-
- demu_state.seq = DEMU_SEQ_PORT_ARRAY_ALLOCATED;
- }
-
- if (demu_state.seq >= DEMU_SEQ_PORT_ARRAY_ALLOCATED) {
- DBG("<PORT_ARRAY_ALLOCATED\n");
-
free(demu_state.ioreq_local_port);
demu_state.seq = DEMU_SEQ_SERVER_ENABLED;
if (demu_state.seq == DEMU_SEQ_SERVER_ENABLED) {
DBG("<SERVER_ENABLED\n");
- (void) xc_hvm_set_ioreq_server_state(demu_state.xch,
- demu_state.domid,
- demu_state.ioservid,
- 0);
+ (void) xendevicemodel_set_ioreq_server_state(demu_state.xdh,
+ demu_state.domid,
+ demu_state.ioservid,
+ 0);
demu_state.seq = DEMU_SEQ_BUFFERED_IOPAGE_MAPPED;
}
if (demu_state.seq >= DEMU_SEQ_SERVER_REGISTERED) {
DBG("<SERVER_REGISTERED\n");
- (void) xc_hvm_destroy_ioreq_server(demu_state.xch,
- demu_state.domid,
- demu_state.ioservid);
- demu_state.seq = DEMU_SEQ_INTERFACE_OPEN;
+ (void) xendevicemodel_destroy_ioreq_server(demu_state.xdh,
+ demu_state.domid,
+ demu_state.ioservid);
+ demu_state.seq = DEMU_SEQ_XENDEVICEMODEL_OPEN;
+ }
+
+ if (demu_state.seq >= DEMU_SEQ_XENDEVICEMODEL_OPEN) {
+ DBG("<XENDEVICEMODEL_OPEN\n");
+
+ xendevicemodel_close(demu_state.xdh);
+
+ demu_state.seq = DEMU_SEQ_XENFOREIGNMEMORY_OPEN;
+ }
+
+ if (demu_state.seq >= DEMU_SEQ_XENFOREIGNMEMORY_OPEN) {
+ DBG("<XENFOREIGNMEMORY_OPEN\n");
+
+ xenforeignmemory_close(demu_state.xfh);
+
+ demu_state.seq = DEMU_SEQ_XENEVTCHN_OPEN;
+ }
+
+ if (demu_state.seq >= DEMU_SEQ_XENEVTCHN_OPEN) {
+ DBG("<XENEVTCHN_OPEN\n");
+
+ xenevtchn_close(demu_state.xeh);
+
+ demu_state.seq = DEMU_SEQ_XENCTRL_OPEN;
}
- if (demu_state.seq >= DEMU_SEQ_INTERFACE_OPEN) {
- DBG("<INTERFACE_OPEN\n");
+ if (demu_state.seq >= DEMU_SEQ_XENCTRL_OPEN) {
+ DBG("<XENCTRL_OPEN\n");
xc_interface_close(demu_state.xch);
static int
demu_initialize(domid_t domid, unsigned int device, unsigned int function)
{
- int rc;
- xc_dominfo_t dominfo;
- unsigned long pfn;
- unsigned long buf_pfn;
- evtchn_port_t port;
- evtchn_port_t buf_port;
- int i;
+ int rc;
+ xc_dominfo_t dominfo;
+ unsigned long pfn;
+ unsigned long buf_pfn;
+ evtchn_port_t port;
+ evtchn_port_t buf_port;
+ int i;
demu_state.domid = domid;
demu_seq_next();
+ demu_state.xeh = xenevtchn_open(NULL, 0);
+ if (demu_state.xeh == NULL)
+ goto fail2;
+
+ demu_seq_next();
+
+ demu_state.xfh = xenforeignmemory_open(NULL, 0);
+ if (demu_state.xfh == NULL)
+ goto fail3;
+
+ demu_seq_next();
+
+ demu_state.xdh = xendevicemodel_open(NULL, 0);
+ if (demu_state.xdh == NULL)
+ goto fail4;
+
+ demu_seq_next();
+
rc = xc_domain_getinfo(demu_state.xch, demu_state.domid, 1, &dominfo);
if (rc < 0 || dominfo.domid != demu_state.domid)
- goto fail2;
+ goto fail5;
demu_state.vcpus = dominfo.max_vcpu_id + 1;
DBG("%d vCPU(s)\n", demu_state.vcpus);
- rc = xc_hvm_create_ioreq_server(demu_state.xch, demu_state.domid, 1,
- &demu_state.ioservid);
+ rc = xendevicemodel_create_ioreq_server(demu_state.xdh,
+ demu_state.domid, 1,
+ &demu_state.ioservid);
if (rc < 0)
- goto fail3;
+ goto fail6;
demu_seq_next();
- rc = xc_hvm_get_ioreq_server_info(demu_state.xch, demu_state.domid,
- demu_state.ioservid, &pfn, &buf_pfn, &buf_port);
+ rc = xendevicemodel_get_ioreq_server_info(demu_state.xdh,
+ demu_state.domid,
+ demu_state.ioservid, &pfn,
+ &buf_pfn, &buf_port);
if (rc < 0)
- goto fail4;
+ goto fail7;
- demu_state.iopage = xc_map_foreign_range(demu_state.xch,
+ demu_state.iopage = xenforeignmemory_map(demu_state.xfh,
demu_state.domid,
- XC_PAGE_SIZE,
PROT_READ | PROT_WRITE,
- pfn);
+ 1, &pfn, NULL);
if (demu_state.iopage == NULL)
- goto fail5;
+ goto fail8;
demu_seq_next();
- demu_state.buffered_iopage = xc_map_foreign_range(demu_state.xch,
+ demu_state.buffered_iopage = xenforeignmemory_map(demu_state.xfh,
demu_state.domid,
- XC_PAGE_SIZE,
- PROT_READ | PROT_WRITE,
- buf_pfn);
+ PROT_READ |
+ PROT_WRITE, 1,
+ &buf_pfn, NULL);
if (demu_state.buffered_iopage == NULL)
- goto fail6;
+ goto fail9;
demu_seq_next();
- rc = xc_hvm_set_ioreq_server_state(demu_state.xch,
- demu_state.domid,
- demu_state.ioservid,
- 1);
+ rc = xendevicemodel_set_ioreq_server_state(demu_state.xdh,
+ demu_state.domid,
+ demu_state.ioservid,
+ 1);
if (rc != 0)
- goto fail7;
+ goto fail10;
demu_seq_next();
demu_state.ioreq_local_port = malloc(sizeof (evtchn_port_t) *
demu_state.vcpus);
if (demu_state.ioreq_local_port == NULL)
- goto fail8;
+ goto fail11;
for (i = 0; i < demu_state.vcpus; i++)
demu_state.ioreq_local_port[i] = -1;
demu_seq_next();
- demu_state.xceh = xc_evtchn_open(NULL, 0);
- if (demu_state.xceh == NULL)
- goto fail9;
-
- demu_seq_next();
-
for (i = 0; i < demu_state.vcpus; i++) {
port = demu_state.iopage->vcpu_ioreq[i].vp_eport;
- rc = xc_evtchn_bind_interdomain(demu_state.xceh, demu_state.domid,
+ rc = xenevtchn_bind_interdomain(demu_state.xeh, demu_state.domid,
port);
if (rc < 0)
- goto fail10;
+ goto fail12;
demu_state.ioreq_local_port[i] = rc;
}
demu_seq_next();
- rc = xc_evtchn_bind_interdomain(demu_state.xceh, demu_state.domid,
+ rc = xenevtchn_bind_interdomain(demu_state.xeh, demu_state.domid,
buf_port);
if (rc < 0)
- goto fail11;
+ goto fail13;
demu_state.buf_ioreq_local_port = rc;
demu_seq_next();
- rc = device_initialize(demu_state.xch, demu_state.domid,
+ rc = device_initialize(demu_state.xdh, demu_state.domid,
demu_state.ioservid, 0, device, function);
if (rc < 0)
- goto fail12;
+ goto fail14;
demu_seq_next();
assert(demu_state.seq == DEMU_SEQ_INITIALIZED);
return 0;
+fail14:
+ DBG("fail14\n");
+
+fail13:
+ DBG("fail13\n");
+
fail12:
DBG("fail12\n");
return;
for (;;) {
- unsigned int read_pointer;
- unsigned int write_pointer;
+ unsigned int read_pointer;
+ unsigned int write_pointer;
read_pointer = demu_state.buffered_iopage->read_pointer;
write_pointer = demu_state.buffered_iopage->write_pointer;
break;
while (read_pointer != write_pointer) {
- unsigned int slot;
- buf_ioreq_t *buf_ioreq;
- ioreq_t ioreq;
+ unsigned int slot;
+ buf_ioreq_t *buf_ioreq;
+ ioreq_t ioreq;
slot = read_pointer % IOREQ_BUFFER_SLOT_NUM;
static void
demu_poll_iopage(unsigned int i)
{
- ioreq_t *ioreq;
+ ioreq_t *ioreq;
if (demu_state.seq != DEMU_SEQ_INITIALIZED)
return;
ioreq->state = STATE_IORESP_READY;
mb();
- xc_evtchn_notify(demu_state.xceh, demu_state.ioreq_local_port[i]);
+ xenevtchn_notify(demu_state.xeh, demu_state.ioreq_local_port[i]);
}
static void
demu_poll_iopages(void)
{
- evtchn_port_t port;
- int i;
+ evtchn_port_t port;
+ int i;
if (demu_state.seq != DEMU_SEQ_INITIALIZED)
return;
- port = xc_evtchn_pending(demu_state.xceh);
+ port = xenevtchn_pending(demu_state.xeh);
if (port < 0)
return;
if (port == demu_state.buf_ioreq_local_port) {
- xc_evtchn_unmask(demu_state.xceh, port);
+ xenevtchn_unmask(demu_state.xeh, port);
demu_poll_buffered_iopage();
} else {
for (i = 0; i < demu_state.vcpus; i++) {
if (port == demu_state.ioreq_local_port[i]) {
- xc_evtchn_unmask(demu_state.xceh, port);
+ xenevtchn_unmask(demu_state.xeh, port);
demu_poll_iopage(i);
}
}
int
main(int argc, char **argv, char **envp)
{
- char *domain_str;
- char *device_str;
- char *function_str;
- int index;
- char *end;
- domid_t domid;
- unsigned int device;
- unsigned int function;
- sigset_t block;
- struct pollfd pfd;
- int rc;
+ char *domain_str;
+ char *device_str;
+ char *function_str;
+ int index;
+ char *end;
+ domid_t domid;
+ unsigned int device;
+ unsigned int function;
+ sigset_t block;
+ struct pollfd pfd;
+ int rc;
prog = basename(argv[0]);
exit(1);
}
- pfd.fd = xc_evtchn_fd(demu_state.xceh);
+ pfd.fd = xenevtchn_fd(demu_state.xeh);
pfd.events = POLLIN | POLLERR | POLLHUP;
pfd.revents = 0;
#define FALSE 0
typedef struct _device_io_state {
- unsigned int index;
- unsigned int order;
+ unsigned int index;
+ unsigned int order;
} device_io_state_t;
-static device_io_state_t device_io_state;
+static device_io_state_t device_io_state;
static void
device_io_map(void *priv, uint64_t addr)
{
- device_io_state_t *state = priv;
+ device_io_state_t *state = priv;
DBG("%d: %016"PRIx64" - %016"PRIx64"\n",
state->index,
static void
device_io_unmap(void *priv)
{
- device_io_state_t *state = priv;
+ device_io_state_t *state = priv;
DBG("%d\n", state->index);
}
{
}
-static bar_ops_t device_io_ops = {
+static bar_ops_t device_io_ops = {
.map = device_io_map,
.unmap = device_io_unmap,
.readb = device_io_readb,
};
typedef struct _device_memory_state {
- unsigned int index;
- unsigned int order;
+ unsigned int index;
+ unsigned int order;
} device_memory_state_t;
-static device_memory_state_t device_memory_state;
+static device_memory_state_t device_memory_state;
static void
device_memory_map(void *priv, uint64_t addr)
{
- device_memory_state_t *state = priv;
+ device_memory_state_t *state = priv;
DBG("%d: %016"PRIx64" - %016"PRIx64"\n",
state->index,
static void
device_memory_unmap(void *priv)
{
- device_memory_state_t *state = priv;
+ device_memory_state_t *state = priv;
DBG("%d\n", state->index);
}
{
}
-static bar_ops_t device_memory_ops = {
+static bar_ops_t device_memory_ops = {
.map = device_memory_map,
.unmap = device_memory_unmap,
.readb = device_memory_readb,
};
int
-device_initialize(xc_interface *xch, domid_t domid, ioservid_t ioservid,
- unsigned int bus, unsigned int device, unsigned int function)
+device_initialize(xendevicemodel_handle *xdh, domid_t domid,
+ ioservid_t ioservid, unsigned int bus,
+ unsigned int device, unsigned int function)
{
- pci_info_t info;
- int rc;
+ pci_info_t info;
+ int rc;
info.bus = bus;
info.device = device;
info.command = PCI_COMMAND_IO;
info.interrupt_pin = 1;
- rc = pci_device_register(xch, domid, ioservid, &info);
+ rc = pci_device_register(xdh, domid, ioservid, &info);
if (rc < 0)
goto fail1;
#include <sys/types.h>
#include <xenctrl.h>
+#include <xendevicemodel.h>
#include "debug.h"
#include "pci.h"
typedef struct pci_bar {
const bar_ops_t *ops;
- int is_mmio;
- int enable;
- uint32_t addr;
- uint32_t size;
- void *priv;
+ int is_mmio;
+ int enable;
+ uint32_t addr;
+ uint32_t size;
+ void *priv;
} pci_bar_t;
typedef struct pci {
- xc_interface *xch;
- domid_t domid;
- ioservid_t ioservid;
- uint16_t bdf;
- uint8_t config[PCI_CONFIG_SIZE];
- uint8_t mask[PCI_CONFIG_SIZE];
- pci_bar_t bar[PCI_NUM_BAR];
- uint32_t irq_pin;
- uint32_t irq_state;
+ xendevicemodel_handle *xdh;
+ domid_t domid;
+ ioservid_t ioservid;
+ uint16_t bdf;
+ uint8_t config[PCI_CONFIG_SIZE];
+ uint8_t mask[PCI_CONFIG_SIZE];
+ pci_bar_t bar[PCI_NUM_BAR];
+ uint32_t irq_pin;
+ uint32_t irq_state;
} pci_t;
-static pci_t pci;
+static pci_t pci;
int
-pci_device_register(xc_interface *xch, domid_t domid, ioservid_t ioservid,
- const pci_info_t *info)
+pci_device_register(xendevicemodel_handle *xdh, domid_t domid,
+ ioservid_t ioservid, const pci_info_t *info)
{
- int rc;
+ int rc;
- pci.xch = xch;
+ pci.xdh = xdh;
pci.domid = domid;
pci.ioservid = ioservid;
DBG("%02x:%02x:%02x\n", info->bus, info->device, info->function);
- rc = xc_hvm_map_pcidev_to_ioreq_server(xch, domid, ioservid,
- 0, info->bus, info->device, info->function);
+ rc = xendevicemodel_map_pcidev_to_ioreq_server(xdh, domid, ioservid,
+ 0, info->bus,
+ info->device,
+ info->function);
if (rc < 0)
goto fail2;
DBG("%02x:%02x:%02x\n", bus, device, function);
- (void) xc_hvm_unmap_pcidev_from_ioreq_server(pci.xch, pci.domid, pci.ioservid,
- 0, bus, device, function);
+ (void) xendevicemodel_unmap_pcidev_from_ioreq_server(pci.xdh, pci.domid,
+ pci.ioservid,
+ 0, bus, device,
+ function);
}
int
pci_bar_register(unsigned int index, uint8_t type, unsigned int order,
const bar_ops_t *ops, void *priv)
{
- pci_bar_t *bar;
+ pci_bar_t *bar;
DBG("%d: %08x\n", index, 1u << order);
bar->size = 1u << order;
*(uint32_t *)&pci.config[PCI_BASE_ADDRESS_0 + (index * 4)] = type;
- *(uint32_t *)&pci.mask[PCI_BASE_ADDRESS_0 + (index * 4)] = ~(bar->size - 1);
+ *(uint32_t *)&pci.mask[PCI_BASE_ADDRESS_0 + (index * 4)] =
+ ~(bar->size - 1);
bar->enable = 1;
bar->addr = PCI_BAR_UNMAPPED;
if (bar->addr == PCI_BAR_UNMAPPED)
return;
- (void) xc_hvm_unmap_io_range_from_ioreq_server(pci.xch,
- pci.domid,
- pci.ioservid,
- bar->is_mmio,
- bar->addr,
- bar->addr + bar->size - 1);
+ (void) xendevicemodel_unmap_io_range_from_ioreq_server(pci.xdh,
+ pci.domid,
+ pci.ioservid,
+ bar->is_mmio,
+ bar->addr,
+ bar->addr +
+ bar->size - 1);
}
static pci_bar_t *
uint32_t
pci_bar_read(int is_mmio, uint64_t addr, uint64_t size)
{
- pci_bar_t *bar = pci_bar_get(is_mmio, addr);
- uint32_t val = 0;
+ pci_bar_t *bar = pci_bar_get(is_mmio, addr);
+ uint32_t val = 0;
assert(bar != NULL);
#define PCI_BAR_WRITE(_fn, _priv, _addr, _size, _count, _val) \
do { \
- int _i = 0; \
- unsigned int _shift = 0; \
+ int _i = 0; \
+ unsigned int _shift = 0; \
\
(_val) = 0; \
for (_i = 0; _i < (_count); _i++) \
void
pci_bar_write(int is_mmio, uint64_t addr, uint64_t size, uint32_t val)
{
- pci_bar_t *bar = pci_bar_get(is_mmio, addr);
+ pci_bar_t *bar = pci_bar_get(is_mmio, addr);
assert(bar != NULL);
if (bar->ops->map)
bar->ops->map(bar->priv, bar->addr);
- (void) xc_hvm_map_io_range_to_ioreq_server(pci.xch,
- pci.domid,
- pci.ioservid,
- bar->is_mmio,
- bar->addr,
- bar->addr + bar->size - 1);
+ (void) xendevicemodel_map_io_range_to_ioreq_server(pci.xdh,
+ pci.domid,
+ pci.ioservid,
+ bar->is_mmio,
+ bar->addr,
+ bar->addr +
+ bar->size - 1);
}
static void
DBG("%d\n", index);
- (void) xc_hvm_unmap_io_range_from_ioreq_server(pci.xch,
- pci.domid,
- pci.ioservid,
- bar->is_mmio,
- bar->addr,
- bar->addr + bar->size - 1);
+ (void) xendevicemodel_unmap_io_range_from_ioreq_server(pci.xdh,
+ pci.domid,
+ pci.ioservid,
+ bar->is_mmio,
+ bar->addr,
+ bar->addr +
+ bar->size - 1);
if (bar->ops->unmap)
bar->ops->unmap(bar->priv);
pci_update_bar(unsigned int index)
{
pci_bar_t *bar = &pci.bar[index];
- uint32_t addr = *(uint32_t *)&pci.config[PCI_BASE_ADDRESS_0 + (index * 4)];
+ uint32_t addr = *(uint32_t *)&pci.config[PCI_BASE_ADDRESS_0 +
+ (index * 4)];
uint16_t cmd = *(uint16_t *)&pci.config[PCI_COMMAND];
uint32_t mask = ~(bar->size - 1);
uint32_t
pci_config_read(uint64_t addr, uint64_t size)
{
- uint64_t i;
- uint32_t val;
- uint32_t sbdf;
+ uint64_t i;
+ uint32_t val;
+ uint32_t sbdf;
sbdf = (uint32_t)(addr >> 32);
void
pci_config_write(uint64_t addr, uint64_t size, uint32_t val)
{
- uint64_t i;
- uint8_t mask;
- uint32_t sbdf;
+ uint64_t i;
+ uint8_t mask;
+ uint32_t sbdf;
sbdf = (uint16_t)(addr >> 32);
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
-#include <linux/pci_regs.h>
-
#ifndef _PCI_H
#define _PCI_H
+#include <linux/pci_regs.h>
+#include <xenctrl.h>
+#include <xendevicemodel.h>
+
#define PCI_NUM_BAR 6
#define PCI_CONFIG_HEADER_SIZE 0x40
#define PCI_CONFIG_SIZE 0x100
#define PCI_BAR_UNMAPPED (~(0u))
typedef struct pci_info {
- uint8_t bus;
- uint8_t device:5;
- uint8_t function:3;
- uint16_t vendor_id;
- uint16_t device_id;
- uint16_t subvendor_id;
- uint16_t subdevice_id;
- uint8_t revision;
- uint8_t class;
- uint8_t subclass;
- uint8_t prog_if;
- uint8_t header_type;
- uint16_t command;
- uint8_t interrupt_pin;
+ uint8_t bus;
+ uint8_t device:5;
+ uint8_t function:3;
+ uint16_t vendor_id;
+ uint16_t device_id;
+ uint16_t subvendor_id;
+ uint16_t subdevice_id;
+ uint8_t revision;
+ uint8_t class;
+ uint8_t subclass;
+ uint8_t prog_if;
+ uint8_t header_type;
+ uint16_t command;
+ uint8_t interrupt_pin;
} pci_info_t;
-int pci_device_register(xc_interface *xch, domid_t domid, ioservid_t ioservid,
- const pci_info_t *info);
-void pci_device_deregister(void);
+int pci_device_register(xendevicemodel_handle *xdh, domid_t domid,
+ ioservid_t ioservid, const pci_info_t *info);
+void pci_device_deregister(void);
typedef struct bar_ops {
- void (*map)(void *priv, uint64_t addr);
- void (*unmap)(void *priv);
- uint8_t (*readb)(void *priv, uint64_t offset);
- uint16_t (*readw)(void *priv, uint64_t offset);
- uint32_t (*readl)(void *priv, uint64_t offset);
- void (*writeb)(void *priv, uint64_t offset, uint8_t val);
- void (*writew)(void *priv, uint64_t offset, uint16_t val);
- void (*writel)(void *priv, uint64_t offset, uint32_t val);
+ void (*map)(void *priv, uint64_t addr);
+ void (*unmap)(void *priv);
+ uint8_t (*readb)(void *priv, uint64_t offset);
+ uint16_t (*readw)(void *priv, uint64_t offset);
+ uint32_t (*readl)(void *priv, uint64_t offset);
+ void (*writeb)(void *priv, uint64_t offset, uint8_t val);
+ void (*writew)(void *priv, uint64_t offset, uint16_t val);
+ void (*writel)(void *priv, uint64_t offset, uint32_t val);
} bar_ops_t;
-int pci_bar_register(unsigned int index, uint8_t type, unsigned int order,
- const bar_ops_t *ops, void *priv);
-void pci_bar_deregister(unsigned int index);
+int pci_bar_register(unsigned int index, uint8_t type, unsigned int order,
+ const bar_ops_t *ops, void *priv);
+void pci_bar_deregister(unsigned int index);
-uint32_t pci_bar_read(int is_mmio, uint64_t addr, uint64_t size);
-void pci_bar_write(int is_mmio, uint64_t addr, uint64_t size, uint32_t val);
+uint32_t pci_bar_read(int is_mmio, uint64_t addr, uint64_t size);
+void pci_bar_write(int is_mmio, uint64_t addr, uint64_t size, uint32_t val);
-uint32_t pci_config_read(uint64_t addr, uint64_t size);
-void pci_config_write(uint64_t addr, uint64_t size, uint32_t val);
-void pci_config_dump();
+uint32_t pci_config_read(uint64_t addr, uint64_t size);
+void pci_config_write(uint64_t addr, uint64_t size, uint32_t val);
+void pci_config_dump();
#endif /* _PCI_H */
projects / people / pauldu / demu.git / commitdiff