acpi: sync FADT flags from PIIX4 to Q35

The following commits updated the FADT flags for PIIX4:
commit c7be281b3be0f2013aa4b5d5f400981a1adb6e63
    Drop FIX_RTC flag from FADT.
commit a4e2b9adbba95c2d783761e84444bbb3c8d6107b
    enable USE_PLATFORM_CLOCK bit in FADT flags

Q35 support was originally written before these commits in seabios, PIIX
got updated, Q35 didn't.  QEMU uses the same clock for both so there's
no reason for these bits to differ.  Sync them up.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
(cherry picked from commit ed88f6515c18d9520efa4a41ccb70038dfbe43f9)

diff --git a/src/acpi.c b/src/acpi.c
index ce988e0c12d38e25dd1acdd81f1172bf89fa9cd2..3699898c2525a9d5b2d5242c780c014d11c78f4b 100644 (file)
--- a/src/acpi.c
+++ b/src/acpi.c
@@ -86,9 +86,9 @@ void ich9_lpc_fadt_setup(struct pci_device *dev, void *arg)
     fadt->gpe0_blk_len = ICH9_PMIO_GPE0_BLK_LEN;
     fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
     fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
-    /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC + RTC_S4 */
-    fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6) |
-                              (1 << 7));
+    /* WBINVD + PROC_C1 + SLP_BUTTON + RTC_S4 + USE_PLATFORM_CLOCK */
+    fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 7) |
+                              (1 << 15));
 }
 
 static const struct pci_device_id fadt_init_tbl[] = {