]> xenbits.xensource.com Git - xen.git/commitdiff
xen/arm: acpi: Relax hw domain mapping attributes to p2m_mmio_direct_c
authorEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Thu, 26 Jan 2017 13:16:02 +0000 (14:16 +0100)
committerStefano Stabellini <sstabellini@kernel.org>
Thu, 16 Mar 2017 20:58:14 +0000 (13:58 -0700)
Since the hardware domain is a trusted domain, we extend the
trust to include making final decisions on what attributes to
use when mapping memory regions.

For ACPI configured hardware domains, this patch relaxes the hardware
domains mapping attributes to p2m_mmio_direct_c. This will allow the
hardware domain to control the attributes via its S1 mappings.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Acked-by: Julien Grall <julien.grall@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>
xen/arch/arm/p2m.c
xen/include/public/memory.h

index fab140d48d79bb2fb5ddbe52ed77b9c35f1eadf5..da6dee58ac12f4a94a7a5339ba409998d0430b93 100644 (file)
@@ -1179,7 +1179,7 @@ int map_dev_mmio_region(struct domain *d,
     if ( !(nr && iomem_access_permitted(d, mfn_x(mfn), mfn_x(mfn) + nr - 1)) )
         return 0;
 
-    res = map_mmio_regions(d, gfn, nr, mfn);
+    res = p2m_insert_mapping(d, gfn, nr, mfn, p2m_mmio_direct_c);
     if ( res < 0 )
     {
         printk(XENLOG_G_ERR "Unable to map MFNs [%#"PRI_mfn" - %#"PRI_mfn" in Dom%d\n",
index 5bf840fe1693d12808f81d4b6c682937ae54739e..315a4e8b1aa15e5ac620e06b999a5f6ef9e07193 100644 (file)
@@ -222,9 +222,9 @@ DEFINE_XEN_GUEST_HANDLE(xen_machphys_mapping_t);
                                     * XENMEM_add_to_physmap_batch only. */
 #define XENMAPSPACE_dev_mmio     5 /* device mmio region
                                       ARM only; the region is mapped in
-                                      Stage-2 using the memory attribute
-                                      "Device-nGnRE" (previously named
-                                      "Device" on ARMv7) */
+                                      Stage-2 using the Normal Memory
+                                      Inner/Outer Write-Back Cacheable
+                                      memory attribute. */
 /* ` } */
 
 /*