/* Do not enable Monitor Trap Flag unless start single step debug */
v->arch.hvm.vmx.exec_control &= ~CPU_BASED_MONITOR_TRAP_FLAG;
- if ( !has_vlapic(d) )
- {
- /* Disable virtual apics, TPR */
- v->arch.hvm.vmx.secondary_exec_control &=
- ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
- | SECONDARY_EXEC_APIC_REGISTER_VIRT
- | SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
- v->arch.hvm.vmx.exec_control &= ~CPU_BASED_TPR_SHADOW;
-
- /* In turn, disable posted interrupts. */
- __vmwrite(PIN_BASED_VM_EXEC_CONTROL,
- vmx_pin_based_exec_control & ~PIN_BASED_POSTED_INTERRUPT);
- }
-
vmx_update_cpu_exec_control(v);
__vmwrite(VM_EXIT_CONTROLS, vmexit_ctl);
gfn_t gfn = gaddr_to_gfn(APIC_DEFAULT_PHYS_BASE);
bool ipat;
- if ( !has_vlapic(d) || mfn_eq(apic_access_mfn, INVALID_MFN) )
+ if ( mfn_eq(apic_access_mfn, INVALID_MFN) )
return;
ASSERT(epte_get_entry_emt(d, gfn, apic_access_mfn, 0, &ipat,
{
paddr_t virt_page_ma, apic_page_ma;
- if ( !has_vlapic(v->domain) || mfn_eq(apic_access_mfn, INVALID_MFN) )
+ if ( mfn_eq(apic_access_mfn, INVALID_MFN) )
return;
ASSERT(cpu_has_vmx_virtualize_apic_accesses);