*pval = value;
}
+static inline u32 __n2_pin_exec_control(struct vcpu *v)
+{
+ struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
+
+ return __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL);
+}
+
static inline u32 __n2_exec_control(struct vcpu *v)
{
struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v);
shadow_cntrl = __get_vvmcs(nvcpu->nv_vvmcx, PIN_BASED_VM_EXEC_CONTROL);
- shadow_cntrl &= ~PIN_BASED_PREEMPT_TIMER;
shadow_cntrl |= host_cntrl;
__vmwrite(PIN_BASED_VM_EXEC_CONTROL, shadow_cntrl);
}
GUEST_INTERRUPTIBILITY_INFO,
GUEST_ACTIVITY_STATE,
GUEST_SYSENTER_CS,
+ GUEST_PREEMPTION_TIMER,
/* natural */
GUEST_ES_BASE,
GUEST_CS_BASE,
break;
case MSR_IA32_VMX_PINBASED_CTLS:
/* 1-seetings */
- data = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
+ data = PIN_BASED_EXT_INTR_MASK |
+ PIN_BASED_NMI_EXITING |
+ PIN_BASED_PREEMPT_TIMER;
data <<= 32;
/* 0-settings */
data |= 0;
if ( ctrl & SECONDARY_EXEC_DESCRIPTOR_TABLE_EXITING )
nvcpu->nv_vmexit_pending = 1;
break;
+ case EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED:
+ ctrl = __n2_pin_exec_control(v);
+ if ( ctrl & PIN_BASED_PREEMPT_TIMER )
+ nvcpu->nv_vmexit_pending = 1;
+ break;
/* L1 has priority handling several other types of exits */
case EXIT_REASON_HLT:
ctrl = __n2_exec_control(v);
GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
GUEST_ACTIVITY_STATE = 0x00004826,
GUEST_SYSENTER_CS = 0x0000482A,
+ GUEST_PREEMPTION_TIMER = 0x0000482e,
HOST_SYSENTER_CS = 0x00004c00,
CR0_GUEST_HOST_MASK = 0x00006000,
CR4_GUEST_HOST_MASK = 0x00006002,