]> xenbits.xensource.com Git - xen.git/commitdiff
xen/x86: add a function for modifying cr3
authorJuergen Gross <jgross@suse.com>
Thu, 26 Apr 2018 11:33:11 +0000 (13:33 +0200)
committerJan Beulich <jbeulich@suse.com>
Tue, 29 May 2018 09:27:57 +0000 (11:27 +0200)
Instead of having multiple places with more or less identical asm
statements just have one function doing a write to cr3.

As this function should be named write_cr3() rename the current
write_cr3() function to switch_cr3().

Suggested-by: Andrew Copper <andrew.cooper3@citrix.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/flushtlb.c
xen/arch/x86/mm.c
xen/arch/x86/x86_64/traps.c
xen/common/efi/runtime.c
xen/include/asm-x86/flushtlb.h
xen/include/asm-x86/processor.h

index 96e5003d797fe91da11eedd513c4f287725fb125..d9941f424988cb78a7d3b2d49c7a3f055085a0a7 100644 (file)
@@ -73,7 +73,7 @@ static void post_flush(u32 t)
     this_cpu(tlbflush_time) = t;
 }
 
-void write_cr3(unsigned long cr3)
+void switch_cr3(unsigned long cr3)
 {
     unsigned long flags, cr4;
     u32 t;
@@ -85,7 +85,7 @@ void write_cr3(unsigned long cr3)
     cr4 = read_cr4();
 
     write_cr4(cr4 & ~X86_CR4_PGE);
-    asm volatile ( "mov %0, %%cr3" : : "r" (cr3) : "memory" );
+    write_cr3(cr3);
     write_cr4(cr4);
 
     post_flush(t);
index 87db8a815861187ce47ae8b4f0c91e82c39ac57b..ffbab0262bc48acc0fba4aa7d57d410ddd507286 100644 (file)
@@ -489,7 +489,7 @@ void make_cr3(struct vcpu *v, unsigned long mfn)
 void write_ptbase(struct vcpu *v)
 {
     get_cpu_info()->root_pgt_changed = 1;
-    write_cr3(v->arch.cr3);
+    switch_cr3(v->arch.cr3);
 }
 
 /*
index 717e51cae3c1b637416697755b765651da36481c..371fa9472cb547a09a8f526600802e12bf4c9cca 100644 (file)
@@ -266,7 +266,7 @@ void toggle_guest_mode(struct vcpu *v)
     get_cpu_info()->root_pgt_changed = 1;
 
     /* Don't flush user global mappings from the TLB. Don't tick TLB clock. */
-    asm volatile ( "mov %0, %%cr3" : : "r" (v->arch.cr3) : "memory" );
+    write_cr3(v->arch.cr3);
 
     if ( !(v->arch.flags & TF_kernel_mode) )
         return;
index b10b15e5238d9167de624ff088bfd80fcfded180..593cc46f10b29c5f21007548b64bf762c84625f1 100644 (file)
@@ -104,7 +104,7 @@ struct efi_rs_state efi_rs_enter(void)
         asm volatile ( "lgdt %0" : : "m" (gdt_desc) );
     }
 
-    write_cr3(virt_to_maddr(efi_l4_pgtable));
+    switch_cr3(virt_to_maddr(efi_l4_pgtable));
 
     return state;
 }
@@ -113,7 +113,7 @@ void efi_rs_leave(struct efi_rs_state *state)
 {
     if ( !state->cr3 )
         return;
-    write_cr3(state->cr3);
+    switch_cr3(state->cr3);
     if ( is_pv_vcpu(current) && !is_idle_vcpu(current) )
     {
         struct desc_ptr gdt_desc = {
index ecc944c717ac18f9da8ccc689a0b51a04972833b..f4b4306dbf74df61ced1c31e6dfcf824b6125119 100644 (file)
@@ -84,7 +84,7 @@ static inline unsigned long read_cr3(void)
 }
 
 /* Write pagetable base and implicitly tick the tlbflush clock. */
-void write_cr3(unsigned long cr3);
+void switch_cr3(unsigned long cr3);
 
 /* flush_* flag fields: */
  /*
index d31b628e0df3a5cae59eda4d2d413fdc1f5d22f2..6f3e65bd95dd63b2edffa02818d5063e75aadef1 100644 (file)
@@ -329,6 +329,11 @@ static inline unsigned long read_cr2(void)
     return cr2;
 }
 
+static inline void write_cr3(unsigned long val)
+{
+    asm volatile ( "mov %0, %%cr3" : : "r" (val) : "memory" );
+}
+
 static inline unsigned long read_cr4(void)
 {
     return get_cpu_info()->cr4;