#define CTX_ASSERT(sc,f) mtx_assert(&(sc)->ctx_lock, (f))
struct mtx ctx_lock;
- struct {
- uint32_t ldb;
- uint32_t ldb_mask;
- uint32_t bar4_xlat;
- uint32_t bar5_xlat;
- uint32_t spad_local;
- uint32_t spci_cmd;
- } reg_ofs;
uint32_t ppd;
uint8_t conn_type;
uint8_t dev_type;
.mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 },
};
+static const struct ntb_alt_reg soc_pri_reg = {
+ .db_bell = SOC_PDOORBELL_OFFSET,
+ .db_mask = SOC_PDBMSK_OFFSET,
+ .spad = SOC_SPAD_OFFSET,
+};
+
static const struct ntb_alt_reg soc_b2b_reg = {
.db_bell = SOC_B2B_DOORBELL_OFFSET,
.spad = SOC_B2B_SPAD_OFFSET,
.mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 },
};
+static const struct ntb_alt_reg xeon_pri_reg = {
+ .db_bell = XEON_PDOORBELL_OFFSET,
+ .db_mask = XEON_PDBMSK_OFFSET,
+ .spad = XEON_SPAD_OFFSET,
+};
+
static const struct ntb_alt_reg xeon_b2b_reg = {
.db_bell = XEON_B2B_DOORBELL_OFFSET,
.spad = XEON_B2B_SPAD_OFFSET,
(uintmax_t)(val & ~ntb->db_valid_mask),
(uintmax_t)ntb->db_valid_mask));
- if (regoff == ntb->reg_ofs.ldb_mask)
+ if (regoff == ntb->self_reg->db_mask)
DB_MASK_ASSERT(ntb, MA_OWNED);
if (ntb->type == NTB_SOC) {
DB_MASK_LOCK(ntb);
ntb->db_mask |= bits;
- db_iowrite(ntb, ntb->reg_ofs.ldb_mask, ntb->db_mask);
+ db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask);
DB_MASK_UNLOCK(ntb);
}
DB_MASK_LOCK(ntb);
ntb->db_mask &= ~bits;
- db_iowrite(ntb, ntb->reg_ofs.ldb_mask, ntb->db_mask);
+ db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask);
DB_MASK_UNLOCK(ntb);
}
ntb_db_read(struct ntb_softc *ntb)
{
- return (db_ioread(ntb, ntb->reg_ofs.ldb));
+ return (db_ioread(ntb, ntb->self_reg->db_bell));
}
void
(uintmax_t)(bits & ~ntb->db_valid_mask),
(uintmax_t)ntb->db_valid_mask));
- db_iowrite(ntb, ntb->reg_ofs.ldb, bits);
+ db_iowrite(ntb, ntb->self_reg->db_bell, bits);
}
static inline uint64_t
{
int rc;
- ntb->reg_ofs.ldb = XEON_PDOORBELL_OFFSET;
- ntb->reg_ofs.ldb_mask = XEON_PDBMSK_OFFSET;
- ntb->reg_ofs.spad_local = XEON_SPAD_OFFSET;
- ntb->reg_ofs.bar4_xlat = XEON_SBAR4XLAT_OFFSET;
- if (HAS_FEATURE(NTB_SPLIT_BAR))
- ntb->reg_ofs.bar5_xlat = XEON_SBAR5XLAT_OFFSET;
- ntb->reg_ofs.spci_cmd = XEON_PCICMD_OFFSET;
-
ntb->spad_count = XEON_SPAD_COUNT;
ntb->db_count = XEON_DB_COUNT;
ntb->db_link_mask = XEON_DB_LINK_BIT;
}
ntb->reg = &xeon_reg;
+ ntb->self_reg = &xeon_pri_reg;
ntb->peer_reg = &xeon_b2b_reg;
ntb->xlat_reg = &xeon_sec_xlat;
return (rc);
/* Enable Bus Master and Memory Space on the secondary side */
- ntb_reg_write(2, ntb->reg_ofs.spci_cmd,
+ ntb_reg_write(2, XEON_PCICMD_OFFSET,
PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
/* Enable link training */
KASSERT(ntb->conn_type == NTB_CONN_B2B,
("Unsupported NTB configuration (%d)\n", ntb->conn_type));
- ntb->reg_ofs.ldb = SOC_PDOORBELL_OFFSET;
- ntb->reg_ofs.ldb_mask = SOC_PDBMSK_OFFSET;
- ntb->reg_ofs.bar4_xlat = SOC_SBAR4XLAT_OFFSET;
- ntb->reg_ofs.spad_local = SOC_SPAD_OFFSET;
- ntb->reg_ofs.spci_cmd = SOC_PCICMD_OFFSET;
-
ntb->spad_count = SOC_SPAD_COUNT;
ntb->db_count = SOC_DB_COUNT;
ntb->db_vec_count = SOC_DB_MSIX_VECTOR_COUNT;
ntb->db_valid_mask = (1ull << ntb->db_count) - 1;
ntb->reg = &soc_reg;
+ ntb->self_reg = &soc_pri_reg;
ntb->peer_reg = &soc_b2b_reg;
ntb->xlat_reg = &soc_sec_xlat;
configure_soc_secondary_side_bars(ntb);
/* Enable Bus Master and Memory Space on the secondary side */
- ntb_reg_write(2, ntb->reg_ofs.spci_cmd,
+ ntb_reg_write(2, SOC_PCICMD_OFFSET,
PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
/* Initiate PCI-E link training */
ntb->ntb_ctl = ntb_cntl;
ntb->lnk_sta = ntb_reg_read(4, ntb->reg->lnk_sta);
} else {
- db_iowrite(ntb, ntb->reg_ofs.ldb, ntb->db_link_mask);
+ db_iowrite(ntb, ntb->self_reg->db_bell, ntb->db_link_mask);
reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2);
if (reg_val == ntb->lnk_sta)
if (idx >= ntb->spad_count)
return (EINVAL);
- ntb_reg_write(4, ntb->reg_ofs.spad_local + idx * 4, val);
+ ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val);
return (0);
}
if (idx >= ntb->spad_count)
return (EINVAL);
- *val = ntb_reg_read(4, ntb->reg_ofs.spad_local + idx * 4);
+ *val = ntb_reg_read(4, ntb->self_reg->spad + idx * 4);
return (0);
}