vcpu_unblock(current);
}
-unsigned int domain_max_vcpus(const struct domain *d)
-{
- /*
- * Since evtchn_init would call domain_max_vcpus for poll_mask
- * allocation when the vgic_ops haven't been initialised yet,
- * we return MAX_VIRT_CPUS if d->arch.vgic.handler is null.
- */
- if ( !d->arch.vgic.handler )
- return MAX_VIRT_CPUS;
- else
- return min_t(unsigned int, MAX_VIRT_CPUS,
- d->arch.vgic.handler->max_vcpus);
-}
-
/*
* Local variables:
* mode: C
clear_bit(virq, d->arch.vgic.allocated_irqs);
}
+unsigned int vgic_max_vcpus(const struct domain *d)
+{
+ /*
+ * Since evtchn_init would call domain_max_vcpus for poll_mask
+ * allocation when the vgic_ops haven't been initialised yet,
+ * we return MAX_VIRT_CPUS if d->arch.vgic.handler is null.
+ */
+ if ( !d->arch.vgic.handler )
+ return MAX_VIRT_CPUS;
+ else
+ return min_t(unsigned int, MAX_VIRT_CPUS,
+ d->arch.vgic.handler->max_vcpus);
+}
+
/*
* Local variables:
* mode: C
void vcpu_show_registers(const struct vcpu *);
void vcpu_switch_to_aarch64_mode(struct vcpu *);
-unsigned int domain_max_vcpus(const struct domain *);
+/* On ARM, the number of VCPUs is limited by the type of GIC emulated. */
+static inline unsigned int domain_max_vcpus(const struct domain *d)
+{
+ return vgic_max_vcpus(d);
+}
/*
* Due to the restriction of GICv3, the number of vCPUs in AFF0 is
extern void vgic_free_virq(struct domain *d, unsigned int virq);
+unsigned int vgic_max_vcpus(const struct domain *d);
+
void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
paddr_t vbase, uint32_t aliased_offset);