octeontx2-af: add mbox for CPT LF reset

[ Upstream commit f58cf765e8f5f4860ea094aa12c156d9195a4c28 ]

On OcteonTX2 SoC, the admin function (AF) is the only one with all
priviliges to configure HW and alloc resources, PFs and it's VFs
have to request AF via mailbox for all their needs.
This patch adds a new mailbox for CPT VFs to request for CPT LF
reset.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Stable-dep-of: a88e0f936ba9 ("octeontx2: Detect the mbox up or down message via register")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index 03ebabd61635383f1723e046da0a476f29c732ea..5decd1919de039de0877d191265cdbe73fec886e 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -196,6 +196,7 @@ M(CPT_STATS,            0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp)   \
 M(CPT_RXC_TIME_CFG,     0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req,  \
                               msg_rsp)                                 \
 M(CPT_CTX_CACHE_SYNC,   0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp)    \
+M(CPT_LF_RESET,         0xA08, cpt_lf_reset, cpt_lf_rst_req, msg_rsp)  \
 /* SDP mbox IDs (range 0x1000 - 0x11FF) */                             \
 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
@@ -1702,6 +1703,13 @@ struct cpt_inst_lmtst_req {
        u64 rsvd;
 };
 
+/* Mailbox message format to request for CPT LF reset */
+struct cpt_lf_rst_req {
+       struct mbox_msghdr hdr;
+       u32 slot;
+       u32 rsvd;
+};
+
 struct sdp_node_info {
        /* Node to which this PF belons to */
        u8 node_id;

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
index 1ed16ce515bb10285264733976c04e2c716f653b..1cd34914cb86bd5ec1899c537b64becbc09dcb76 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
@@ -851,6 +851,39 @@ int rvu_mbox_handler_cpt_ctx_cache_sync(struct rvu *rvu, struct msg_req *req,
        return rvu_cpt_ctx_flush(rvu, req->hdr.pcifunc);
 }
 
+int rvu_mbox_handler_cpt_lf_reset(struct rvu *rvu, struct cpt_lf_rst_req *req,
+                                 struct msg_rsp *rsp)
+{
+       u16 pcifunc = req->hdr.pcifunc;
+       struct rvu_block *block;
+       int cptlf, blkaddr, ret;
+       u16 actual_slot;
+       u64 ctl, ctl2;
+
+       blkaddr = rvu_get_blkaddr_from_slot(rvu, BLKTYPE_CPT, pcifunc,
+                                           req->slot, &actual_slot);
+       if (blkaddr < 0)
+               return CPT_AF_ERR_LF_INVALID;
+
+       block = &rvu->hw->block[blkaddr];
+
+       cptlf = rvu_get_lf(rvu, block, pcifunc, actual_slot);
+       if (cptlf < 0)
+               return CPT_AF_ERR_LF_INVALID;
+       ctl = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf));
+       ctl2 = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf));
+
+       ret = rvu_lf_reset(rvu, block, cptlf);
+       if (ret)
+               dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
+                       block->addr, cptlf);
+
+       rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), ctl);
+       rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), ctl2);
+
+       return 0;
+}
+
 static void cpt_rxc_teardown(struct rvu *rvu, int blkaddr)
 {
        struct cpt_rxc_time_cfg_req req;