arch/arm64: Fix `ukarch_tlb_flush_entry`

Fix a bug in `ukarch_tlb_flush_entry` that leads to the TLB entry
not being invalidated on arm64.

The argument `X` of `tlbi vaae1is, X` is not the virtual address,
but a field that contains the bits 55:12 of the virtual address in
the bits 43:0. The remaining bits of this field (RES0,TTL) are valid
being set to 0.

Store the virtual address at the proper location in the argument.

Signed-off-by: Robert Kuban <robert.kuban@opensynergy.com>

diff --git a/arch/arm/arm64/include/uk/asm/paging.h b/arch/arm/arm64/include/uk/asm/paging.h
index 19b58ddd508e42e046fa0b31292cadd141ce4402..fdd9ef25f6396db5ee2f6b9235797674d74768c6 100644 (file)
--- a/arch/arm/arm64/include/uk/asm/paging.h
+++ b/arch/arm/arm64/include/uk/asm/paging.h
@@ -285,12 +285,13 @@ static inline int ukarch_pt_write_base(__paddr_t pt_paddr)
 
 static inline void ukarch_tlb_flush_entry(__vaddr_t vaddr)
 {
+       __u64 page_number = vaddr >> PAGE_SHIFT;
        __asm__ __volatile__(
                "       dsb     ishst\n"        /* wait for write complete */
                "       tlbi    vaae1is, %x0\n" /* invalidate by vaddr */
                "       dsb     ish\n"          /* wait for invalidate compl */
                "       isb\n"                  /* sync context */
-               :: "r" (vaddr) : "memory");
+               :: "r" (page_number) : "memory");
 }
 
 static inline void ukarch_tlb_flush(void)