--- /dev/null
+/** @file\r
+ CPUCFG definitions.\r
+\r
+ Copyright (c) 2024, Loongson Technology Corporation Limited. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+\r
+#ifndef CPUCFG_H_\r
+#define CPUCFG_H_\r
+\r
+/**\r
+ CPUCFG REG0 Information\r
+\r
+ @code\r
+ CPUCFG_REG0_INFO_DATA\r
+ **/\r
+#define CPUCFG_REG0_INFO 0x0\r
+\r
+/**\r
+ CPUCFG REG0 Information returned data.\r
+ #CPUCFG_REG0_INFO\r
+ **/\r
+typedef union {\r
+ struct {\r
+ ///\r
+ /// [Bit 31:0] Processor Identity.\r
+ ///\r
+ UINT32 PRID : 32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUCFG_REG0_INFO_DATA;\r
+\r
+/**\r
+ CPUCFG REG1 Information\r
+\r
+ @code\r
+ CPUCFG_REG1_INFO_DATA\r
+ **/\r
+#define CPUCFG_REG1_INFO 0x1\r
+\r
+/**\r
+ CPUCFG REG1 Information returned data.\r
+ #CPUCFG_REG1_INFO\r
+ **/\r
+typedef union {\r
+ struct {\r
+ ///\r
+ /// [Bit 1:0] Architecture:\r
+ /// 2'b00 indicates the implementation of simplified LoongAarch32;\r
+ /// 2'b01 indicates the implementation of LoongAarch32;\r
+ /// 2'b10 indicates the implementation of LoongAarch64;\r
+ /// 2'b11 reserved;\r
+ ///\r
+ UINT32 ARCH : 2;\r
+ ///\r
+ /// [Bit 2] Paging mapping mode. A value of 1 indicates the processor MMU supports\r
+ /// page mapping mode.\r
+ ///\r
+ UINT32 PGMMU : 1;\r
+ ///\r
+ /// [Bit 3] A value of 1 indicates the processor supports the IOCSR instruction.\r
+ ///\r
+ UINT32 IOCSR : 1;\r
+ ///\r
+ /// [Bit 11:4] Physical address bits. The supported physical address bits PALEN value\r
+ /// minus 1.\r
+ ///\r
+ UINT32 PALEN : 8;\r
+ ///\r
+ /// [Bit 19:12] Virtual address bits. The supported virtual address bits VALEN value\r
+ /// minus 1.\r
+ ///\r
+ UINT32 VALEN : 8;\r
+ ///\r
+ /// [Bit 20] Non-aligned Memory Access. A value of 1 indicates the processor supports\r
+ /// non-aligned memory access.\r
+ ///\r
+ UINT32 UAL : 1;\r
+ ///\r
+ /// [Bit 21] Page Read Inhibit. A value of 1 indicates the processor supports page\r
+ /// attribute of "Read Inhibit".\r
+ ///\r
+ UINT32 RI : 1;\r
+ ///\r
+ /// [Bit 22] Page Execution Protection. A value of 1 indicates the processor supports\r
+ /// page attribute of "Execution Protection".\r
+ ///\r
+ UINT32 EP : 1;\r
+ ///\r
+ /// [Bit 23] A value of 1 indicates the processor supports for page attributes of RPLV.\r
+ ///\r
+ UINT32 RPLV : 1;\r
+ ///\r
+ /// [Bit 24] Huge Page. A value of 1 indicates the processor supports page attribute\r
+ /// of huge page.\r
+ ///\r
+ UINT32 HP : 1;\r
+ ///\r
+ /// [Bit 25] A value of 1 indicates that the string of processor product information\r
+ /// is recorded at address 0 of the IOCSR access space.\r
+ ///\r
+ UINT32 IOCSR_BRD : 1;\r
+ ///\r
+ /// [Bit 26] A value of 1 indicates that the external interrupt uses the message\r
+ /// interrupt mode, otherwise it is the level interrupt line mode.\r
+ ///\r
+ UINT32 MSG_INT : 1;\r
+ ///\r
+ /// [Bit 31:27] Reserved.\r
+ ///\r
+ UINT32 Reserved : 5;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUCFG_REG1_INFO_DATA;\r
+\r
+/**\r
+ CPUCFG REG2 Information\r
+\r
+ @code\r
+ CPUCFG_REG2_INFO_DATA\r
+ **/\r
+#define CPUCFG_REG2_INFO 0x2\r
+\r
+/**\r
+ CPUCFG REG2 Information returned data.\r
+ #CPUCFG_REG2_INFO\r
+ **/\r
+typedef union {\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Basic Floating-Point. A value of 1 indicates the processor supports basic\r
+ /// floating-point instructions.\r
+ ///\r
+ UINT32 FP : 1;\r
+ ///\r
+ /// [Bit 1] Sigle-Precision. A value of 1 indicates the processor supports sigle-precision\r
+ /// floating-point numbers.\r
+ ///\r
+ UINT32 FP_SP : 1;\r
+ ///\r
+ /// [Bit 2] Double-Precision. A value of 1 indicates the processor supports double-precision\r
+ /// floating-point numbers.\r
+ ///\r
+ UINT32 FP_DP : 1;\r
+ ///\r
+ /// [Bit 5:3] The version number of the floating-point arithmetic standard. 1 is the initial\r
+ /// version number, indicating that it is compatible with the IEEE 754-2008 standard.\r
+ ///\r
+ UINT32 FP_ver : 3;\r
+ ///\r
+ /// [Bit 6] 128-bit Vector Extension. A value of 1 indicates the processor supports 128-bit\r
+ /// vector extension.\r
+ ///\r
+ UINT32 LSX : 1;\r
+ ///\r
+ /// [Bit 7] 256-bit Vector Extension. A value of 1 indicates the processor supports 256-bit\r
+ /// vector extension.\r
+ ///\r
+ UINT32 LASX : 1;\r
+ ///\r
+ /// [Bit 8] Complex Vector Operation Instructions. A value of 1 indicates the processor supports\r
+ /// complex vector operation instructions.\r
+ ///\r
+ UINT32 COMPLEX : 1;\r
+ ///\r
+ /// [Bit 9] Encryption And Decryption Vector Instructions. A value of 1 indicates the processor\r
+ /// supports encryption and decryption vector instructions.\r
+ ///\r
+ UINT32 CRYPTO : 1;\r
+ ///\r
+ /// [Bit 10] Virtualization Expansion. A value of 1 indicates the processor supports\r
+ /// virtualization expansion.\r
+ ///\r
+ UINT32 LVZ : 1;\r
+ ///\r
+ /// [Bit 13:11] The version number of the virtualization hardware acceleration specification.\r
+ /// 1 is the initial version number.\r
+ ///\r
+ UINT32 LVZ_ver : 3;\r
+ ///\r
+ /// [Bit 14] Constant Frequency Counter And Timer. A value of 1 indicates the processor supports\r
+ /// constant frequency counter and timer.\r
+ ///\r
+ UINT32 LLFTP : 1;\r
+ ///\r
+ /// [Bit 17:15] Constant frequency counter and timer version number. 1 is the initial version.\r
+ ///\r
+ UINT32 LLTP_ver : 3;\r
+ ///\r
+ /// [Bit 18] X86 Binary Translation Extension. A value of 1 indicates the processor supports\r
+ /// X86 binary translation extension.\r
+ ///\r
+ UINT32 LBT_X86 : 1;\r
+ ///\r
+ /// [Bit 19] ARM Binary Translation Extension. A value of 1 indicates the processor supports\r
+ /// ARM binary translation extension.\r
+ ///\r
+ UINT32 LBT_ARM : 1;\r
+ ///\r
+ /// [Bit 20] MIPS Binary Translation Extension. A value of 1 indicates the processor supports\r
+ /// MIPS binary translation extension.\r
+ ///\r
+ UINT32 LBT_MIPS : 1;\r
+ ///\r
+ /// [Bit 21] Software Page Table Walking Instruction. A value of 1 indicates the processor\r
+ /// supports software page table walking instruction.\r
+ ///\r
+ UINT32 LSPW : 1;\r
+ ///\r
+ /// [Bit 22] Atomic Memory Access Instruction. A value of 1 indicates the processor supports\r
+ /// AM* atomic memory access instruction.\r
+ ///\r
+ UINT32 LAM : 1;\r
+ ///\r
+ /// [Bit 31:23] Reserved.\r
+ ///\r
+ UINT32 Reserved : 9;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUCFG_REG2_INFO_DATA;\r
+\r
+/**\r
+ CPUCFG REG3 Information\r
+\r
+ @code\r
+ CPUCFG_REG3_INFO_DATA\r
+ **/\r
+#define CPUCFG_REG3_INFO 0x3\r
+\r
+/**\r
+ CPUCFG REG3 Information returned data.\r
+ #CPUCFG_REG3_INFO\r
+ **/\r
+typedef union {\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Hardware Cache Coherent DMA. A value of 1 indicates the processor supports\r
+ /// hardware cache coherent DMA.\r
+ ///\r
+ UINT32 CCDMA : 1;\r
+ ///\r
+ /// [Bit 1] Store Fill Buffer. A value of 1 indicates the processor supports store fill\r
+ /// buffer (SFB).\r
+ ///\r
+ UINT32 SFB : 1;\r
+ ///\r
+ /// [Bit 2] Uncache Accelerate. A value of 1 indicates the processor supports uncache\r
+ /// accelerate.\r
+ ///\r
+ UINT32 UCACC : 1;\r
+ ///\r
+ /// [Bit 3] A value of 1 indicates the processor supports LL instruction to fetch exclusive\r
+ /// block function.\r
+ ///\r
+ UINT32 LLEXC : 1;\r
+ ///\r
+ /// [Bit 4] A value of 1 indicates the processor supports random delay function after SC\r
+ /// instruction.\r
+ ///\r
+ UINT32 SCDLY : 1;\r
+ ///\r
+ /// [Bit 5] A value of 1 indicates the processor supports LL automatic with dbar function.\r
+ ///\r
+ UINT32 LLDBAR : 1;\r
+ ///\r
+ /// [Bit 6] A value of 1 indicates the processor supports the hardware maintains the\r
+ /// consistency between ITLB and TLB.\r
+ ///\r
+ UINT32 ITLBT : 1;\r
+ ///\r
+ /// [Bit 7] A value of 1 indicates the processor supports the hardware maintains the data\r
+ /// consistency between ICache and DCache in one processor core.\r
+ ///\r
+ UINT32 ICACHET : 1;\r
+ ///\r
+ /// [Bit 10:8] The maximum number of directory levels supported by the page walk instruction.\r
+ ///\r
+ UINT32 SPW_LVL : 3;\r
+ ///\r
+ /// [Bit 11] A value of 1 indicates the processor supports the page walk instruction fills\r
+ /// the TLB in half when it encounters a large page.\r
+ ///\r
+ UINT32 SPW_HP_HF : 1;\r
+ ///\r
+ /// [Bit 12] Virtual Address Range. A value of 1 indicates the processor supports the software\r
+ /// configuration can be used to shorten the virtual address range.\r
+ ///\r
+ UINT32 RVA : 1;\r
+ ///\r
+ /// [Bit 16:13] The maximum configurable virtual address is shortened by -1.\r
+ ///\r
+ UINT32 RVAMAX_1 : 4;\r
+ ///\r
+ /// [Bit 31:17] Reserved.\r
+ ///\r
+ UINT32 Reserved : 15;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUCFG_REG3_INFO_DATA;\r
+\r
+/**\r
+ CPUCFG REG4 Information\r
+\r
+ @code\r
+ CPUCFG_REG4_INFO_DATA\r
+ **/\r
+#define CPUCFG_REG4_INFO 0x4\r
+\r
+/**\r
+ CPUCFG REG4 Information returned data.\r
+ #CPUCFG_REG4_INFO\r
+ **/\r
+typedef union {\r
+ struct {\r
+ ///\r
+ /// [Bit 31:0] Constant frequency timer and the crystal frequency corresponding to the clock\r
+ /// used by the timer.\r
+ ///\r
+ UINT32 CC_FREQ : 32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUCFG_REG4_INFO_DATA;\r
+\r
+/**\r
+ CPUCFG REG5 Information\r
+\r
+ @code\r
+ CPUCFG_REG5_INFO_DATA\r
+ **/\r
+#define CPUCFG_REG5_INFO 0x5\r
+\r
+/**\r
+ CPUCFG REG5 Information returned data.\r
+ #CPUCFG_REG5_INFO\r
+ **/\r
+typedef union {\r
+ struct {\r
+ ///\r
+ /// [Bit 15:0] Constant frequency timer and the corresponding multiplication factor of the\r
+ /// clock used by the timer.\r
+ ///\r
+ UINT32 CC_MUL : 16;\r
+ ///\r
+ /// [Bit 31:16] Constant frequency timer and the division coefficient corresponding to the\r
+ /// clock used by the timer\r
+ ///\r
+ UINT32 CC_DIV : 16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUCFG_REG5_INFO_DATA;\r
+\r
+/**\r
+ CPUCFG REG6 Information\r
+\r
+ @code\r
+ CPUCFG_REG6_INFO_DATA\r
+ **/\r
+#define CPUCFG_REG6_INFO 0x6\r
+\r
+/**\r
+ CPUCFG REG6 Information returned data.\r
+ #CPUCFG_REG6_INFO\r
+ **/\r
+typedef union {\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Performance Counter. A value of 1 indicates the processor supports performance\r
+ /// counter.\r
+ ///\r
+ UINT32 PMP : 1;\r
+ ///\r
+ /// [Bit 3:1] In the performance monitor, the architecture defines the version number of the\r
+ /// event, and 1 is the initial version\r
+ ///\r
+ UINT32 PMVER : 3;\r
+ ///\r
+ /// [Bit 7:4] Number of performance monitors minus 1.\r
+ ///\r
+ UINT32 PMNUM : 4;\r
+ ///\r
+ /// [Bit 13:8] Number of bits of a performance monitor minus 1.\r
+ ///\r
+ UINT32 PMBITS : 6;\r
+ ///\r
+ /// [Bit 14] A value of 1 indicates the processor supports reading performance counter in user mode.\r
+ ///\r
+ UINT32 UPM : 1;\r
+ ///\r
+ /// [Bit 31:15] Reserved.\r
+ ///\r
+ UINT32 Reserved : 17;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUCFG_REG6_INFO_DATA;\r
+\r
+/**\r
+ CPUCFG REG16 Information\r
+\r
+ @code\r
+ CPUCFG_REG16_INFO_DATA\r
+ **/\r
+#define CPUCFG_REG16_INFO 0x10\r
+\r
+/**\r
+ CPUCFG REG16 Information returned data.\r
+ #CPUCFG_REG16_INFO\r
+ **/\r
+typedef union {\r
+ struct {\r
+ ///\r
+ /// [Bit 0] A value of 1 indicates the processor has a first-level instruction cache\r
+ /// or a first-level unified cache\r
+ ///\r
+ UINT32 L1_IU_Present : 1;\r
+ ///\r
+ /// [Bit 1] A value of 1 indicates that the cache shown by L1 IU_Present is the\r
+ /// unified cache.\r
+ ///\r
+ UINT32 L1_IU_Unify : 1;\r
+ ///\r
+ /// [Bit 2] A value of 1 indicates the processor has a first-level data cache.\r
+ ///\r
+ UINT32 L1_D_Present : 1;\r
+ ///\r
+ /// [Bit 3] A value of 1 indicates the processor has a second-level instruction cache\r
+ /// or a second-level unified cache.\r
+ ///\r
+ UINT32 L2_IU_Present : 1;\r
+ ///\r
+ /// [Bit 4] A value of 1 indicates that the cache shown by L2 IU_Present is the\r
+ /// unified cache.\r
+ ///\r
+ UINT32 L2_IU_Unify : 1;\r
+ ///\r
+ /// [Bit 5] A value of 1 indicates that the cache shown by L2 IU_Present is private\r
+ /// to each core.\r
+ ///\r
+ UINT32 L2_IU_Private : 1;\r
+ ///\r
+ /// [Bit 6] A value of 1 indicates that the cache shown by L2 IU_Present has an inclusive\r
+ /// relationship to the lower levels (L1).\r
+ ///\r
+ UINT32 L2_IU_Inclusive : 1;\r
+ ///\r
+ /// [Bit 7] A value of 1 indicates the processor has a second-level data cache.\r
+ ///\r
+ UINT32 L2_D_Present : 1;\r
+ ///\r
+ /// [Bit 8] A value of 1 indicates that the second-level data cache is private to each core.\r
+ ///\r
+ UINT32 L2_D_Private : 1;\r
+ ///\r
+ /// [Bit 9] A value of 1 indicates that the second-level data cache has a containment\r
+ /// relationship to the lower level (L1).\r
+ ///\r
+ UINT32 L2_D_Inclusive : 1;\r
+ ///\r
+ /// [Bit 10] A value of 1 indicates the processor has a three-level instruction cache\r
+ /// or a second-level unified Cache.\r
+ ///\r
+ UINT32 L3_IU_Present : 1;\r
+ ///\r
+ /// [Bit 11] A value of 1 indicates that the cache shown by L3 IU_Present is the\r
+ /// unified cache.\r
+ ///\r
+ UINT32 L3_IU_Unify : 1;\r
+ ///\r
+ /// [Bit 12] A value of 1 indicates that the cache shown by L3 IU_Present is private\r
+ /// to each core.\r
+ ///\r
+ UINT32 L3_IU_Private : 1;\r
+ ///\r
+ /// [Bit 13] A value of 1 indicates that the cache shown by L3 IU_Present has an inclusive\r
+ /// relationship to the lower levels (L1 and L2).\r
+ ///\r
+ UINT32 L3_IU_Inclusive : 1;\r
+ ///\r
+ /// [Bit 14] A value of 1 indicates the processor has a three-level data cache.\r
+ ///\r
+ UINT32 L3_D_Present : 1;\r
+ ///\r
+ /// [Bit 15] A value of 1 indicates that the three-level data cache is private to each core.\r
+ ///\r
+ UINT32 L3_D_Private : 1;\r
+ ///\r
+ /// [Bit 16] A value of 1 indicates that the three-level data cache has a containment\r
+ /// relationship to the lower level (L1 and L2).\r
+ ///\r
+ UINT32 L3_D_Inclusive : 1;\r
+ ///\r
+ /// [Bit 31:17] Reserved.\r
+ ///\r
+ UINT32 Reserved : 15;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUCFG_REG16_INFO_DATA;\r
+\r
+/**\r
+ CPUCFG REG17, REG18, REG19 and REG20 Information\r
+\r
+ @code\r
+ CPUCFG_CACHE_INFO_DATA\r
+ **/\r
+#define CPUCFG_REG17_INFO 0x11 /// L1 unified cache.\r
+#define CPUCFG_REG18_INFO 0x12 /// L1 data cache.\r
+#define CPUCFG_REG19_INFO 0x13 /// L2 unified cache.\r
+#define CPUCFG_REG20_INFO 0x14 /// L3 unified cache.\r
+\r
+/**\r
+ CPUCFG CACHE Information returned data.\r
+ #CPUCFG_REG17_INFO\r
+ #CPUCFG_REG18_INFO\r
+ #CPUCFG_REG19_INFO\r
+ #CPUCFG_REG20_INFO\r
+ **/\r
+typedef union {\r
+ struct {\r
+ ///\r
+ /// [Bit 15:0] Number of channels minus 1.\r
+ ///\r
+ UINT32 Way_1 : 16;\r
+ ///\r
+ /// [Bit 23:16] Log2 (number of cache rows per channel).\r
+ ///\r
+ UINT32 Index_log2 : 8;\r
+ ///\r
+ /// [Bit 30:24] Log2 (cache row bytes).\r
+ ///\r
+ UINT32 Linesize_log2 : 7;\r
+ ///\r
+ /// [Bit 31] Reserved.\r
+ ///\r
+ UINT32 Reserved : 1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUCFG_CACHE_INFO_DATA;\r
+#endif\r
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