x86/msr: Virtualise MSR_SPEC_CTRL.SSBD for guests to use

Almost all infrastructure is already in place.  Update the reserved bits
calculation in guest_wrmsr(), and offer SSBD to guests by default.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
master commit: cd53023df952cf0084be9ee3d15a90f8837049c2
master date: 2018-05-21 14:20:06 +0100

diff --git a/xen/arch/x86/domctl.c b/xen/arch/x86/domctl.c
index 68933878b84b054945cb5779bd08eb4a590533ab..49ca8dd10d6a134885bbfe7409aa6483d51b2512 100644 (file)
--- a/xen/arch/x86/domctl.c
+++ b/xen/arch/x86/domctl.c
@@ -1365,7 +1365,8 @@ long arch_do_domctl(
                      * ignored) when STIBP isn't enumerated in hardware.
                      */
 
-                    if ( msr.value & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+                    if ( msr.value & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
+                                       (boot_cpu_has(X86_FEATURE_SSBD) ? SPEC_CTRL_SSBD : 0)) )
                         break;
                     v->arch.spec_ctrl = msr.value;
                     continue;

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index f62b021c5e7c3c3518b3906d8747fa6d0fd80152..5ba00b22c53a186ea050406bb14e343e08e1dd3d 100644 (file)
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -3991,7 +3991,9 @@ int hvm_msr_write_intercept(unsigned int msr, uint64_t msr_content,
          * when STIBP isn't enumerated in hardware.
          */
 
-        if ( msr_content & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+        if ( msr_content & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
+                             (edx & cpufeat_mask(X86_FEATURE_SSBD)
+                              ? SPEC_CTRL_SSBD : 0)) )
             goto gp_fault; /* Rsvd bit set? */
 
         v->arch.spec_ctrl = msr_content;

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 1e2e7d4a7e03a5b154b8481647d3eb9c9c601471..731d05423e5838a5c7a543c4d8c368a88ec9723c 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2903,7 +2903,9 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
              * when STIBP isn't enumerated in hardware.
              */
 
-            if ( msr_content & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP) )
+            if ( msr_content & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP |
+                                 (edx & cpufeat_mask(X86_FEATURE_SSBD)
+                                  ? SPEC_CTRL_SSBD : 0)) )
                 goto fail; /* Rsvd bit set? */
 
             v->arch.spec_ctrl = eax;

diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index f7116585ea56c06ea9d7cefbbe8652bb5c59efe8..3d57339a9b9c13dd400f50f580596ef071360efa 100644 (file)
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -230,7 +230,7 @@ XEN_CPUFEATURE(IBPB,          8*32+12) /*A  IBPB support only (no IBRS, used by
 XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by Intel) */
 XEN_CPUFEATURE(STIBP,         9*32+27) /*A! STIBP */
 XEN_CPUFEATURE(ARCH_CAPS,     9*32+29) /*   IA32_ARCH_CAPABILITIES MSR */
-XEN_CPUFEATURE(SSBD,          9*32+31) /*   MSR_SPEC_CTRL.SSBD available */
+XEN_CPUFEATURE(SSBD,          9*32+31) /*A  MSR_SPEC_CTRL.SSBD available */
 
 #endif /* XEN_CPUFEATURE */