Add MSR support for various feature AMD processor families.

Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>

diff --git a/xen/arch/x86/apic.c b/xen/arch/x86/apic.c
index 56d820ec031fb58955529c0aaf766572667efbf2..bd3ae1a49a54c0a4a799cc3488af4a4cf7085792 100644 (file)
--- a/xen/arch/x86/apic.c
+++ b/xen/arch/x86/apic.c
@@ -823,7 +823,7 @@ static int __init detect_init_APIC (void)
     switch (boot_cpu_data.x86_vendor) {
     case X86_VENDOR_AMD:
         if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
-            (boot_cpu_data.x86 >= 15 && boot_cpu_data.x86 <= 17))
+            (boot_cpu_data.x86 >= 0xf && boot_cpu_data.x86 <= 0x17))
             break;
         goto no_apic;
     case X86_VENDOR_INTEL:

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 2f959c05d63353b9c1a29f8301aa2c9f9a67dfa6..67a3352dbb6e4562f187981d42a6fa961b305d96 100644 (file)
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -433,10 +433,9 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
        }
 
        switch (c->x86) {
-       case 15:
+       case 0xf:
        /* Use K8 tuning for Fam10h and Fam11h */
-       case 0x10:
-       case 0x11:
+       case 0x10 ... 0x17:
                set_bit(X86_FEATURE_K8, c->x86_capability);
                disable_c1e(NULL);
                if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
@@ -500,7 +499,7 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
 #endif
 
        /* Pointless to use MWAIT on Family10 as it does not deep sleep. */
-       if (c->x86 == 0x10 && !force_mwait)
+       if (c->x86 >= 0x10 && !force_mwait)
                clear_bit(X86_FEATURE_MWAIT, c->x86_capability);
 
        /* K6s reports MCEs but don't actually have all the MSRs */

diff --git a/xen/arch/x86/cpu/mcheck/mce.c b/xen/arch/x86/cpu/mcheck/mce.c
index efbf2d2c4427f860208d6696b1d6c6b94a4e65a7..b94afdc2dd54df74cb5110d8fbfcad934453a420 100644 (file)
--- a/xen/arch/x86/cpu/mcheck/mce.c
+++ b/xen/arch/x86/cpu/mcheck/mce.c
@@ -599,8 +599,7 @@ static enum mcheck_type amd_mcheck_init(struct cpuinfo_x86 *ci)
                rc = amd_k8_mcheck_init(ci);
                break;
 
-       case 0x10:
-       case 0x11:
+       case 0x10 ... 0x17:
                rc = amd_f10_mcheck_init(ci);
                break;
        }

diff --git a/xen/arch/x86/nmi.c b/xen/arch/x86/nmi.c
index f84a8f43a0213bdfdd521eabded2065a18cfc482..ee954adc6a844a1268fbc6032329a1d1047fa10b 100644 (file)
--- a/xen/arch/x86/nmi.c
+++ b/xen/arch/x86/nmi.c
@@ -323,7 +323,7 @@ void __pminit setup_apic_nmi_watchdog(void)
     case X86_VENDOR_AMD:
         switch (boot_cpu_data.x86) {
         case 6:
-        case 15 ... 17:
+        case 0xf ... 0x17:
             setup_k7_watchdog();
             break;
         default:

diff --git a/xen/arch/x86/oprofile/nmi_int.c b/xen/arch/x86/oprofile/nmi_int.c
index 0f543a1f1c4e2abde052fc34d031f1148e25f841..89902575cae8b1db2654d538a67603bf56e0c47b 100644 (file)
--- a/xen/arch/x86/oprofile/nmi_int.c
+++ b/xen/arch/x86/oprofile/nmi_int.c
@@ -448,6 +448,18 @@ static int __init nmi_init(void)
                                model = &op_athlon_spec;
                                cpu_type = "x86-64/family11";
                                break;
+                        case 0x12:
+                               model = &op_athlon_spec;
+                               cpu_type = "x86-64/family12";
+                               break;
+                       case 0x14:
+                                model = &op_athlon_spec;
+                                cpu_type = "x86-64/family14";
+                                break;
+                        case 0x15:
+                                model = &op_athlon_spec;
+                                cpu_type = "x86-64/family15";
+                                break;
                        }
                        break;
  

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index b333958b7b50d5827dca2d04bf20e508a08eac7e..f6ef710154d2044856ee943ccb298605f5d2574b 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2246,7 +2246,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
             break;
         case MSR_AMD64_NB_CFG:
             if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-                 boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 )
+                 boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
                 goto fail;
             if ( !IS_PRIV(v->domain) )
                 break;
@@ -2259,7 +2259,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
             break;
         case MSR_FAM10H_MMIO_CONF_BASE:
             if ( boot_cpu_data.x86_vendor != X86_VENDOR_AMD ||
-                 boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x11 )
+                 boot_cpu_data.x86 < 0x10 || boot_cpu_data.x86 > 0x17 )
                 goto fail;
             if ( !IS_PRIV(v->domain) )
                 break;
@@ -3247,8 +3247,7 @@ void __devinit percpu_traps_init(void)
         switch ( boot_cpu_data.x86 )
         {
         case 6:
-        case 15:
-        case 16:
+        case 0xf ... 0x17:
             this_cpu(ler_msr) = MSR_IA32_LASTINTFROMIP;
             break;
         }