* r1 = machine nr, r2 = atags or dtb pointer.
*...
*/
- regs->r0 = 0; /* SBZ */
- regs->r1 = 0xffffffff; /* We use DTB therefore no machine id */
+ regs->r0 = 0U; /* SBZ */
+ regs->r1 = 0xffffffffU; /* We use DTB therefore no machine id */
regs->r2 = kinfo->dtb_paddr;
}
#ifdef CONFIG_ARM_64
static void PrintMessage(const CHAR16 *s);
#define DEVICE_TREE_GUID \
-{0xb1b621d5, 0xf19c, 0x41a5, {0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0}}
+{0xb1b621d5U, 0xf19c, 0x41a5, {0x83, 0x0b, 0xd9, 0x15, 0x2c, 0x69, 0xaa, 0xe0}}
static struct file __initdata dtbfile;
static void __initdata *fdt;
/* The first 32 interrupts (PPI and SGI) are banked per-cpu, so
* even though they are controlled with GICD registers, they must
* be set up here with the other per-cpu state. */
- writel_gicd(0xffffffff, GICD_ICACTIVER); /* Diactivate PPIs and SGIs */
- writel_gicd(0xffff0000, GICD_ICENABLER); /* Disable all PPI */
- writel_gicd(0x0000ffff, GICD_ISENABLER); /* Enable all SGI */
+ writel_gicd(0xffffffffU, GICD_ICACTIVER); /* De-activate PPIs and SGIs */
+ writel_gicd(0xffff0000U, GICD_ICENABLER); /* Disable all PPI */
+ writel_gicd(0x0000ffffU, GICD_ISENABLER); /* Enable all SGI */
/* Set SGI priorities */
for ( i = 0; i < 16; i += 4 )
/* Disable/deactivate all global interrupts */
for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 )
{
- writel_relaxed(0xffffffff, GICD + GICD_ICENABLER + (i / 32) * 4);
- writel_relaxed(0xffffffff, GICD + GICD_ICACTIVER + (i / 32) * 4);
+ writel_relaxed(0xffffffffU, GICD + GICD_ICENABLER + (i / 32) * 4);
+ writel_relaxed(0xffffffffU, GICD + GICD_ICACTIVER + (i / 32) * 4);
}
/*
* The activate state is unknown at boot, so make sure all
* SGIs and PPIs are de-activated.
*/
- writel_relaxed(0xffffffff, GICD_RDIST_SGI_BASE + GICR_ICACTIVER0);
+ writel_relaxed(0xffffffffU, GICD_RDIST_SGI_BASE + GICR_ICACTIVER0);
/*
* Disable all PPI interrupts, ensure all SGI interrupts are
* enabled.
*/
- writel_relaxed(0xffff0000, GICD_RDIST_SGI_BASE + GICR_ICENABLER0);
- writel_relaxed(0x0000ffff, GICD_RDIST_SGI_BASE + GICR_ISENABLER0);
+ writel_relaxed(0xffff0000U, GICD_RDIST_SGI_BASE + GICR_ICENABLER0);
+ writel_relaxed(0x0000ffffU, GICD_RDIST_SGI_BASE + GICR_ISENABLER0);
/* Configure SGIs/PPIs as non-secure Group-1 */
writel_relaxed(GENMASK(31, 0), GICD_RDIST_SGI_BASE + GICR_IGROUPR0);
* BRK instruction encoding
* The #imm16 value should be placed at bits[20:5] within BRK ins
*/
-#define AARCH64_BREAK_MON 0xd4200000
+#define AARCH64_BREAK_MON 0xd4200000U
/*
* BRK instruction for provoking a fault on purpose
#pragma pack()
#endif
-#define EFIERR(a) (0x8000000000000000 | a)
-#define EFI_ERROR_MASK 0x8000000000000000
-#define EFIERR_OEM(a) (0xc000000000000000 | a)
+#define EFIERR(a) (0x8000000000000000ULL | a)
+#define EFI_ERROR_MASK 0x8000000000000000ULL
+#define EFIERR_OEM(a) (0xc000000000000000ULL | a)
-#define BAD_POINTER 0xFBFBFBFBFBFBFBFB
-#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFF
+#define BAD_POINTER 0xFBFBFBFBFBFBFBFBULL
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
#define EFI_STUB_ERROR MAX_ADDRESS
static always_inline u32 aarch64_insn_get_##abbr##_value(void) \
{ return (val); }
-__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
-__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
-__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
-__AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
-__AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
-__AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
-__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
-__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
+__AARCH64_INSN_FUNCS(b, 0xFC000000U, 0x14000000U)
+__AARCH64_INSN_FUNCS(bl, 0xFC000000U, 0x94000000U)
+__AARCH64_INSN_FUNCS(cbz, 0x7F000000U, 0x34000000U)
+__AARCH64_INSN_FUNCS(cbnz, 0x7F000000U, 0x35000000U)
+__AARCH64_INSN_FUNCS(tbz, 0x7F000000U, 0x36000000U)
+__AARCH64_INSN_FUNCS(tbnz, 0x7F000000U, 0x37000000U)
+__AARCH64_INSN_FUNCS(bcond, 0xFF000010U, 0x54000000U)
+__AARCH64_INSN_FUNCS(hint, 0xFFFFF01FU, 0xD503201FU)
bool aarch64_insn_is_branch_imm(u32 insn);
if ( ret && cp64.read )
{
- set_user_reg(regs, cp64.reg1, x & 0xffffffff);
+ set_user_reg(regs, cp64.reg1, x & 0xffffffffU);
set_user_reg(regs, cp64.reg2, x >> 32);
}
/* There are other fields but we don't use them yet. */
};
-#define DTB_MAGIC 0xd00dfeed
+#define DTB_MAGIC 0xd00dfeedU
/**
* copy_from_paddr - copy data from a physical address
register_t sctlr = READ_SYSREG(SCTLR_EL1);
if ( sctlr & SCTLR_A32_EL1_V )
- return 0xffff0000 + offset;
+ return 0xffff0000U + offset;
else /* always have security exceptions */
return READ_SYSREG(VBAR_EL1) + offset;
}
#ifdef CONFIG_ARM_64
(uint32_t)(ctxt->far >> 32),
ctxt->ifsr32_el2,
- (uint32_t)(ctxt->far & 0xffffffff),
+ (uint32_t)(ctxt->far & 0xffffffffU),
ctxt->esr_el1
#else
ctxt->ifar, ctxt->ifsr, ctxt->dfar, ctxt->dfsr
{
/* Deliberately corrupt parameter regs used by this hypercall. */
switch ( hypercall_args[*nr] ) {
- case 5: HYPERCALL_ARG5(regs) = 0xDEADBEEF;
- case 4: HYPERCALL_ARG4(regs) = 0xDEADBEEF;
- case 3: HYPERCALL_ARG3(regs) = 0xDEADBEEF;
- case 2: HYPERCALL_ARG2(regs) = 0xDEADBEEF;
+ case 5: HYPERCALL_ARG5(regs) = 0xDEADBEEFU;
+ case 4: HYPERCALL_ARG4(regs) = 0xDEADBEEFU;
+ case 3: HYPERCALL_ARG3(regs) = 0xDEADBEEFU;
+ case 2: HYPERCALL_ARG2(regs) = 0xDEADBEEFU;
case 1: /* Don't clobber x0/r0 -- it's the return value */
case 0: /* -ENOSYS case */
break;
default: BUG();
}
- *nr = 0xDEADBEEF;
+ *nr = 0xDEADBEEFU;
}
#endif
case VREG32(GICD_SGIR):
if ( dabt.size != DABT_WORD ) goto bad_width;
/* Write only -- read unknown */
- *r = 0xdeadbeef;
+ *r = 0xdeadbeefU;
return 1;
case VRANGE32(0xF04, 0xF0C):
return 1;
read_unknown:
- *r = vreg_reg64_extract(0xdeadbeafdeadbeaf, info);
+ *r = vreg_reg64_extract(0xdeadbeafdeadbeafULL, info);
return 1;
}
#define XEN_SMCCC_MINOR_REVISION 1
/* Hypervisor Service UID. Randomly generated with uuidgen. */
-#define XEN_SMCCC_UID XEN_DEFINE_UUID(0xa71812dc, 0xc698, 0x4369, 0x9acf, \
+#define XEN_SMCCC_UID XEN_DEFINE_UUID(0xa71812dcU, 0xc698, 0x4369, 0x9acf, \
0x79, 0xd1, 0x8d, 0xde, 0xe6, 0x67)
/* Standard Service Service Call version. */
#define SSSC_SMCCC_MINOR_REVISION 1
/* Standard Service Call UID. Randomly generated with uuidgen. */
-#define SSSC_SMCCC_UID XEN_DEFINE_UUID(0xf863386f, 0x4b39, 0x4cbd, 0x9220,\
+#define SSSC_SMCCC_UID XEN_DEFINE_UUID(0xf863386fU, 0x4b39, 0x4cbd, 0x9220,\
0xce, 0x16, 0x41, 0xe5, 0x9f, 0x6f)
#endif /* __XEN_PUBLIC_ARCH_ARM_SMCCC_H__ */