>> Allows mapping of RuntimeServices which have no cachability attribute
>> set as UC.
-### ept (Intel)
-> `= List of ( {no-}pml | {no-}ad )`
+### ept
+> `= List of [ ad=<bool>, pml=<bool> ]`
-Controls EPT related features.
+> Applicability: Intel
-> Sub-options:
-
-> `pml`
+Extended Page Tables are a feature of Intel's VT-x technology, whereby
+hardware manages the virtualisation of HVM guest pagetables. EPT was
+introduced with the Nehalem architecture.
-> Default: `true`
+* The `ad` boolean controls hardware tracking of Access and Dirty bits in the
+ EPT pagetables, and was first introduced in Broadwell Server.
->> PML is a new hardware feature in Intel's Broadwell Server and further
->> platforms which reduces hypervisor overhead of log-dirty mechanism by
->> automatically recording GPAs (guest physical addresses) when guest memory
->> gets dirty, and therefore significantly reducing number of EPT violation
->> caused by write protection of guest memory, which is a necessity to
->> implement log-dirty mechanism before PML.
+ By default, Xen will use A/D tracking when available in hardware, except
+ on Avoton processors affected by erratum AVR41. Explicitly choosing
+ `ad=0` will disable the use of A/D tracking on capable hardware, whereas
+ choosing `ad=1` will cause tracking to be used even on AVR41-affected
+ hardware.
-> `ad`
+* The `pml` boolean controls the use of Page Modification Logging, which is
+ also introduced in Broadwell Server.
-> Default: Hardware dependent
+ PML is a feature whereby the processor generates a list of pages which
+ have been dirtied. This is necessary information for operations such as
+ live migration, and having the processor maintain the list of dirtied
+ pages is more efficient than traditional software implementations where
+ all guest writes trap into Xen so the dirty bitmap can be maintained.
->> Have hardware keep accessed/dirty (A/D) bits updated.
+ By default, Xen will use PML when it is available in hardware. PML
+ functionally depends on A/D tracking, so choosing `ad=0` will implicitly
+ disable PML. `pml=0` can be used to prevent the use of PML on otherwise
+ capable hardware.
### extra\_guest\_irqs
> `= [<domU number>][,<dom0 number>]`
static unsigned int __read_mostly ple_window = 4096;
integer_param("ple_window", ple_window);
-static bool_t __read_mostly opt_pml_enabled = 1;
+static bool __read_mostly opt_ept_pml = true;
static s8 __read_mostly opt_ept_ad = -1;
-/*
- * The 'ept' parameter controls functionalities that depend on, or impact the
- * EPT mechanism. Optional comma separated value may contain:
- *
- * pml Enable PML
- * ad Use A/D bits
- */
static int __init parse_ept_param(const char *s)
{
const char *ss;
- int rc = 0;
+ int val, rc = 0;
do {
- bool_t val = !!strncmp(s, "no-", 3);
-
- if ( !val )
- s += 3;
-
ss = strchr(s, ',');
if ( !ss )
ss = strchr(s, '\0');
- if ( !strncmp(s, "pml", ss - s) )
- opt_pml_enabled = val;
- else if ( !strncmp(s, "ad", ss - s) )
+ if ( (val = parse_boolean("ad", s, ss)) >= 0 )
opt_ept_ad = val;
+ else if ( (val = parse_boolean("pml", s, ss)) >= 0 )
+ opt_ept_pml = val;
else
rc = -EINVAL;
opt |= SECONDARY_EXEC_ENABLE_VPID;
if ( opt_unrestricted_guest_enabled )
opt |= SECONDARY_EXEC_UNRESTRICTED_GUEST;
- if ( opt_pml_enabled )
+ if ( opt_ept_pml )
opt |= SECONDARY_EXEC_ENABLE_PML;
/*
if ( !(_vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) )
_vmx_secondary_exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
- /* Turn off opt_pml_enabled if PML feature is not present */
+ /* Turn off opt_ept_pml if PML feature is not present. */
if ( !(_vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_PML) )
- opt_pml_enabled = 0;
+ opt_ept_pml = false;
if ( (_vmx_secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) &&
ple_gap == 0 )