case R_ALPHA_BRSGP:
/* PC-relative jump. Tweak offset to skip the two instructions that try to
set up the gp from the pv. */
- fprintf(outfile, " fix_bsr(gen_code_ptr + %ld, (uint8_t *) &%s - (gen_code_ptr + %ld) + 4);\n",
+ fprintf(outfile, " fix_bsr(gen_code_ptr + %ld, (uint8_t *) &%s - (gen_code_ptr + %ld + 4) + 8);\n",
rel->r_offset - start_offset, sym_name, rel->r_offset - start_offset);
break;
default:
is_write, &uc->uc_sigmask);
}
+#elif defined(__alpha__)
+
+int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
+ void *puc)
+{
+ struct ucontext *uc = puc;
+ uint32_t *pc = uc->uc_mcontext.sc_pc;
+ uint32_t insn = *pc;
+ int is_write = 0;
+
+ switch (insn >> 26) {
+ case 0x0d: // stw
+ case 0x0e: // stb
+ case 0x0f: // stq_u
+ case 0x24: // stf
+ case 0x25: // stg
+ case 0x26: // sts
+ case 0x27: // stt
+ case 0x2c: // stl
+ case 0x2d: // stq
+ case 0x2e: // stl_c
+ case 0x2f: // stq_c
+ is_write = 1;
+ }
+
+ return handle_cpu_signal(pc, (unsigned long)info->si_addr,
+ is_write, &uc->uc_sigmask);
+}
#else
#error CPU specific signal handler needed
register unsigned int EAX asm("$12");
register unsigned int ESP asm("$13");
register unsigned int EBP asm("$14");
+/* Note $15 is the frame pointer, so anything in op-i386.c that would
+ require a frame pointer, like alloca, would probably loose. */
register struct CPUX86State *env asm("$15");
#define reg_EAX
#define reg_ESP
#endif
#ifdef __alpha__
-int testandset (int *p)
+static inline int testandset (int *p)
{
int ret;
unsigned long one;
double d;
#ifndef WORDS_BIGENDIAN
struct {
- unsigned long lower;
- long upper;
+ uint32_t lower;
+ int32_t upper;
} l;
#else
struct {
- long upper;
- unsigned long lower;
+ int32_t upper;
+ uint32_t lower;
} l;
#endif
- long long ll;
+ int64_t ll;
} CPU86_LDoubleU;
/* the following deal with IEEE double-precision numbers */