UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.inf

The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit
field PageTableBaseAddress is from bit 12 to bit 52. This means if the
compiler treats the 64bits value as two UINT32 value, the field
PageTableBaseAddress spans two UINT32 value. That's why when building in
NOOPT mode in IA32, the below issue is noticed:
	unresolved external symbol __allshl
This patch fix the build failure by seperate field PageTableBaseAddress
into two fields, make sure no field spans two UINT32 value.

Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Ray Ni <ray.ni@intel.com>

diff --git a/UefiCpuPkg/Include/Library/CpuPageTableLib.h b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
index 352b6df6c68deb4afba06b63496a421841519284..78aa83b8de5f4fd7730363bc35513cfeccc08d38 100644 (file)
--- a/UefiCpuPkg/Include/Library/CpuPageTableLib.h
+++ b/UefiCpuPkg/Include/Library/CpuPageTableLib.h
@@ -11,22 +11,22 @@
 \r
 typedef union {\r
   struct {\r
-    UINT64    Present              : 1; // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64    ReadWrite            : 1; // 0 = Read-Only, 1= Read/Write\r
-    UINT64    UserSupervisor       : 1; // 0 = Supervisor, 1=User\r
-    UINT64    WriteThrough         : 1; // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64    CacheDisabled        : 1; // 0 = Cached, 1=Non-Cached\r
-    UINT64    Accessed             : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64    Dirty                : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)\r
-    UINT64    Pat                  : 1; // PAT\r
-\r
-    UINT64    Global               : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)\r
-    UINT64    Reserved1            : 3; // Ignored\r
-\r
-    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
-    UINT64    Reserved2            : 7;  // Ignored\r
-    UINT64    ProtectionKey        : 4;  // Protection key\r
-    UINT64    Nx                   : 1;  // No Execute bit\r
+    UINT32    Present                  : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT32    ReadWrite                : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT32    UserSupervisor           : 1;  // 0 = Supervisor, 1=User\r
+    UINT32    WriteThrough             : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT32    CacheDisabled            : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT32    Accessed                 : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT32    Dirty                    : 1;  // 0 = Not dirty, 1 = Dirty (set by CPU)\r
+    UINT32    Pat                      : 1;  // PAT\r
+    UINT32    Global                   : 1;  // 0 = Not global, 1 = Global (if CR4.PGE = 1)\r
+    UINT32    Reserved1                : 3;  // Ignored\r
+    UINT32    PageTableBaseAddressLow  : 20; // Page Table Base Address Low\r
+\r
+    UINT32    PageTableBaseAddressHigh : 20; // Page Table Base Address High\r
+    UINT32    Reserved2                : 7;  // Ignored\r
+    UINT32    ProtectionKey            : 4;  // Protection key\r
+    UINT32    Nx                       : 1;  // No Execute bit\r
   } Bits;\r
   UINT64    Uint64;\r
 } IA32_MAP_ATTRIBUTE;\r

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
index 8d856d7c7e2cefc58e8cf5aab64b344c9376d767..2c67ecb46947c127a53e9004e41586f657d0cb36 100644 (file)
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTable.h
@@ -29,11 +29,12 @@ typedef enum {
 } IA32_PAGE_LEVEL;\r
 \r
 typedef struct {\r
-  UINT64    Present        : 1;       // 0 = Not present in memory, 1 = Present in memory\r
-  UINT64    ReadWrite      : 1;       // 0 = Read-Only, 1= Read/Write\r
-  UINT64    UserSupervisor : 1;       // 0 = Supervisor, 1=User\r
-  UINT64    Reserved       : 58;\r
-  UINT64    Nx             : 1;        // No Execute bit\r
+  UINT32    Present        : 1;       // 0 = Not present in memory, 1 = Present in memory\r
+  UINT32    ReadWrite      : 1;       // 0 = Read-Only, 1= Read/Write\r
+  UINT32    UserSupervisor : 1;       // 0 = Supervisor, 1=User\r
+  UINT32    Reserved0      : 29;\r
+  UINT32    Reserved1      : 31;\r
+  UINT32    Nx             : 1;        // No Execute bit\r
 } IA32_PAGE_COMMON_ENTRY;\r
 \r
 ///\r
@@ -41,20 +42,20 @@ typedef struct {
 ///\r
 typedef union {\r
   struct {\r
-    UINT64    Present              : 1; // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64    ReadWrite            : 1; // 0 = Read-Only, 1= Read/Write\r
-    UINT64    UserSupervisor       : 1; // 0 = Supervisor, 1=User\r
-    UINT64    WriteThrough         : 1; // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64    CacheDisabled        : 1; // 0 = Cached, 1=Non-Cached\r
-    UINT64    Accessed             : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64    Available0           : 1; // Ignored\r
-    UINT64    MustBeZero           : 1; // Must Be Zero\r
-\r
-    UINT64    Available2           : 4; // Ignored\r
-\r
-    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
-    UINT64    Available3           : 11; // Ignored\r
-    UINT64    Nx                   : 1;  // No Execute bit\r
+    UINT32    Present                  : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT32    ReadWrite                : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT32    UserSupervisor           : 1;  // 0 = Supervisor, 1=User\r
+    UINT32    WriteThrough             : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT32    CacheDisabled            : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT32    Accessed                 : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT32    Available0               : 1;  // Ignored\r
+    UINT32    MustBeZero               : 1;  // Must Be Zero\r
+    UINT32    Available2               : 4;  // Ignored\r
+    UINT32    PageTableBaseAddressLow  : 20; // Page Table Base Address Low\r
+\r
+    UINT32    PageTableBaseAddressHigh : 20; // Page Table Base Address High\r
+    UINT32    Available3               : 11; // Ignored\r
+    UINT32    Nx                       : 1;  // No Execute bit\r
   } Bits;\r
   UINT64    Uint64;\r
 } IA32_PAGE_NON_LEAF_ENTRY;\r
@@ -86,23 +87,23 @@ typedef IA32_PAGE_NON_LEAF_ENTRY IA32_PDE;
 ///\r
 typedef union {\r
   struct {\r
-    UINT64    Present              : 1; // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64    ReadWrite            : 1; // 0 = Read-Only, 1= Read/Write\r
-    UINT64    UserSupervisor       : 1; // 0 = Supervisor, 1=User\r
-    UINT64    WriteThrough         : 1; // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64    CacheDisabled        : 1; // 0 = Cached, 1=Non-Cached\r
-    UINT64    Accessed             : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64    Dirty                : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)\r
-    UINT64    MustBeOne            : 1; // Page Size. Must Be One\r
-\r
-    UINT64    Global               : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)\r
-    UINT64    Available1           : 3; // Ignored\r
-    UINT64    Pat                  : 1; // PAT\r
-\r
-    UINT64    PageTableBaseAddress : 39; // Page Table Base Address\r
-    UINT64    Available3           : 7;  // Ignored\r
-    UINT64    ProtectionKey        : 4;  // Protection key\r
-    UINT64    Nx                   : 1;  // No Execute bit\r
+    UINT32    Present                  : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT32    ReadWrite                : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT32    UserSupervisor           : 1;  // 0 = Supervisor, 1=User\r
+    UINT32    WriteThrough             : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT32    CacheDisabled            : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT32    Accessed                 : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT32    Dirty                    : 1;  // 0 = Not dirty, 1 = Dirty (set by CPU)\r
+    UINT32    MustBeOne                : 1;  // Page Size. Must Be One\r
+    UINT32    Global                   : 1;  // 0 = Not global, 1 = Global (if CR4.PGE = 1)\r
+    UINT32    Available1               : 3;  // Ignored\r
+    UINT32    Pat                      : 1;  // PAT\r
+    UINT32    PageTableBaseAddressLow  : 19; // Page Table Base Address Low\r
+\r
+    UINT32    PageTableBaseAddressHigh : 20; // Page Table Base Address High\r
+    UINT32    Available3               : 7;  // Ignored\r
+    UINT32    ProtectionKey            : 4;  // Protection key\r
+    UINT32    Nx                       : 1;  // No Execute bit\r
   } Bits;\r
   UINT64    Uint64;\r
 } IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE;\r
@@ -123,22 +124,22 @@ typedef IA32_PAGE_LEAF_ENTRY_BIG_PAGESIZE IA32_PDPTE_1G;
 ///\r
 typedef union {\r
   struct {\r
-    UINT64    Present              : 1; // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64    ReadWrite            : 1; // 0 = Read-Only, 1= Read/Write\r
-    UINT64    UserSupervisor       : 1; // 0 = Supervisor, 1=User\r
-    UINT64    WriteThrough         : 1; // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64    CacheDisabled        : 1; // 0 = Cached, 1=Non-Cached\r
-    UINT64    Accessed             : 1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64    Dirty                : 1; // 0 = Not dirty, 1 = Dirty (set by CPU)\r
-    UINT64    Pat                  : 1; // PAT\r
-\r
-    UINT64    Global               : 1; // 0 = Not global, 1 = Global (if CR4.PGE = 1)\r
-    UINT64    Available1           : 3; // Ignored\r
-\r
-    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
-    UINT64    Available3           : 7;  // Ignored\r
-    UINT64    ProtectionKey        : 4;  // Protection key\r
-    UINT64    Nx                   : 1;  // No Execute bit\r
+    UINT32    Present                  : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT32    ReadWrite                : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT32    UserSupervisor           : 1;  // 0 = Supervisor, 1=User\r
+    UINT32    WriteThrough             : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT32    CacheDisabled            : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT32    Accessed                 : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT32    Dirty                    : 1;  // 0 = Not dirty, 1 = Dirty (set by CPU)\r
+    UINT32    Pat                      : 1;  // PAT\r
+    UINT32    Global                   : 1;  // 0 = Not global, 1 = Global (if CR4.PGE = 1)\r
+    UINT32    Available1               : 3;  // Ignored\r
+    UINT32    PageTableBaseAddressLow  : 20; // Page Table Base Address Low\r
+\r
+    UINT32    PageTableBaseAddressHigh : 20; // Page Table Base Address High\r
+    UINT32    Available3               : 7;  // Ignored\r
+    UINT32    ProtectionKey            : 4;  // Protection key\r
+    UINT32    Nx                       : 1;  // No Execute bit\r
   } Bits;\r
   UINT64    Uint64;\r
 } IA32_PTE_4K;\r
@@ -149,16 +150,16 @@ typedef union {
 ///\r
 typedef union {\r
   struct {\r
-    UINT64    Present              : 1; // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64    MustBeZero           : 2; // Must Be Zero\r
-    UINT64    WriteThrough         : 1; // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64    CacheDisabled        : 1; // 0 = Cached, 1=Non-Cached\r
-    UINT64    MustBeZero2          : 4; // Must Be Zero\r
-\r
-    UINT64    Available            : 3; // Ignored\r
-\r
-    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
-    UINT64    MustBeZero3          : 12; // Must Be Zero\r
+    UINT32    Present                  : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT32    MustBeZero               : 2;  // Must Be Zero\r
+    UINT32    WriteThrough             : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT32    CacheDisabled            : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT32    MustBeZero2              : 4;  // Must Be Zero\r
+    UINT32    Available                : 3;  // Ignored\r
+    UINT32    PageTableBaseAddressLow  : 20; // Page Table Base Address Low\r
+\r
+    UINT32    PageTableBaseAddressHigh : 20; // Page Table Base Address High\r
+    UINT32    MustBeZero3              : 12; // Must Be Zero\r
   } Bits;\r
   UINT64    Uint64;\r
 } IA32_PDPTE_PAE;\r

diff --git a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
index 64383cc522b1b99669822864c4918f4b1f9c1520..7936333e01705f2bcdca5d660403c7cdea5e7497 100644 (file)
--- a/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
+++ b/UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c
@@ -26,7 +26,7 @@ PageTableLibSetPte4K (
   IN IA32_MAP_ATTRIBUTE  *Mask\r
   )\r
 {\r
-  if (Mask->Bits.PageTableBaseAddress) {\r
+  if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddressHigh) {\r
     Pte4K->Uint64 = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) | (Pte4K->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_40);\r
   }\r
 \r
@@ -93,7 +93,7 @@ PageTableLibSetPleB (
   IN IA32_MAP_ATTRIBUTE                 *Mask\r
   )\r
 {\r
-  if (Mask->Bits.PageTableBaseAddress) {\r
+  if (Mask->Bits.PageTableBaseAddressLow || Mask->Bits.PageTableBaseAddressHigh) {\r
     PleB->Uint64 = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) | (PleB->Uint64 & ~IA32_PE_BASE_ADDRESS_MASK_39);\r
   }\r
 \r
@@ -239,7 +239,7 @@ IsAttributesAndMaskValidForNonPresentEntry (
     //\r
     if ((Mask->Bits.ReadWrite == 0) || (Mask->Bits.UserSupervisor == 0) || (Mask->Bits.WriteThrough == 0) || (Mask->Bits.CacheDisabled == 0) ||\r
         (Mask->Bits.Accessed == 0) || (Mask->Bits.Dirty == 0) || (Mask->Bits.Pat == 0) || (Mask->Bits.Global == 0) ||\r
-        (Mask->Bits.PageTableBaseAddress == 0) || (Mask->Bits.ProtectionKey == 0) || (Mask->Bits.Nx == 0))\r
+        ((Mask->Bits.PageTableBaseAddressLow == 0) && (Mask->Bits.PageTableBaseAddressHigh == 0)) || (Mask->Bits.ProtectionKey == 0) || (Mask->Bits.Nx == 0))\r
     {\r
       return RETURN_INVALID_PARAMETER;\r
     }\r
@@ -399,7 +399,7 @@ PageTableLibMapInLevel (
       // This function is called when the memory length is less than the region length of the parent level.\r
       // No need to split the page when the attributes equal.\r
       //\r
-      if (Mask->Bits.PageTableBaseAddress == 0) {\r
+      if ((Mask->Bits.PageTableBaseAddressLow == 0) && (Mask->Bits.PageTableBaseAddressHigh == 0)) {\r
         return RETURN_SUCCESS;\r
       }\r
 \r
@@ -706,7 +706,7 @@ PageTableMap (
     return RETURN_INVALID_PARAMETER;\r
   }\r
 \r
-  if ((LinearAddress % SIZE_4KB != 0) || (Length % SIZE_4KB != 0)) {\r
+  if (((UINTN)LinearAddress % SIZE_4KB != 0) || ((UINTN)Length % SIZE_4KB != 0)) {\r
     //\r
     // LinearAddress and Length should be multiple of 4K.\r
     //\r
@@ -750,12 +750,12 @@ PageTableMap (
 \r
   *IsModified = FALSE;\r
 \r
-  ParentAttribute.Uint64                    = 0;\r
-  ParentAttribute.Bits.PageTableBaseAddress = 1;\r
-  ParentAttribute.Bits.Present              = 1;\r
-  ParentAttribute.Bits.ReadWrite            = 1;\r
-  ParentAttribute.Bits.UserSupervisor       = 1;\r
-  ParentAttribute.Bits.Nx                   = 0;\r
+  ParentAttribute.Uint64                       = 0;\r
+  ParentAttribute.Bits.PageTableBaseAddressLow = 1;\r
+  ParentAttribute.Bits.Present                 = 1;\r
+  ParentAttribute.Bits.ReadWrite               = 1;\r
+  ParentAttribute.Bits.UserSupervisor          = 1;\r
+  ParentAttribute.Bits.Nx                      = 0;\r
 \r
   //\r
   // Query the required buffer size without modifying the page table.\r