MSIX, like PCI, is little endian. Specifying native is wrong here,
but we need to check the rest of the file to determine if it's
as simple as flipping this macro.
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
static const MemoryRegionOps msix_mmio_ops = {
.read = msix_mmio_read,
.write = msix_mmio_write,
+ /* TODO: MSIX should be LITTLE_ENDIAN. */
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,