x86: address violations of MISRA C Rule 8.4

Rule 8.4 states: "A compatible declaration shall be visible when an
object or function with external linkage is defined."

These variables are only referenced from assembly code, so they need to
be extern and there is negligible risk of them being used improperly
without noticing.

As a result, they can be exempted using a comment-based deviation.
No functional change.

Signed-off-by: Nicola Vetrini <nicola.vetrini@bugseng.com>
Acked-by: Jan Beulich <jbeulich@suse.com>

diff --git a/xen/arch/x86/desc.c b/xen/arch/x86/desc.c
index 39080ca672118a169867f0e84e4cfd33526aa7c8..9f639281540a54955bf0b4e194cf1f986b64ab95 100644 (file)
--- a/xen/arch/x86/desc.c
+++ b/xen/arch/x86/desc.c
@@ -91,6 +91,7 @@ seg_desc_t boot_compat_gdt[PAGE_SIZE / sizeof(seg_desc_t)] =
  * References boot_cpu_gdt_table for a short period, until the CPUs switch
  * onto their per-CPU GDTs.
  */
+/* SAF-1-safe */
 const struct desc_ptr boot_gdtr = {
     .limit = LAST_RESERVED_GDT_BYTE,
     .base = (unsigned long)(boot_gdt - FIRST_RESERVED_GDT_ENTRY),

diff --git a/xen/arch/x86/mm.c b/xen/arch/x86/mm.c
index d968bbbc73158b8c74af0b853a8e64eea1f3785b..17987eb5199e31acc311ea085b35e59fe7226c32 100644 (file)
--- a/xen/arch/x86/mm.c
+++ b/xen/arch/x86/mm.c
@@ -144,7 +144,7 @@
 l1_pgentry_t __section(".bss.page_aligned") __aligned(PAGE_SIZE)
     l1_fixmap[L1_PAGETABLE_ENTRIES];
 l1_pgentry_t __section(".bss.page_aligned") __aligned(PAGE_SIZE)
-    l1_fixmap_x[L1_PAGETABLE_ENTRIES];
+    l1_fixmap_x[L1_PAGETABLE_ENTRIES]; /* SAF-1-safe */
 
 bool __read_mostly machine_to_phys_mapping_valid;