int scsi_virtualDev[4] = { -1, -1, -1, -1 };
bool floppy_present[2] = { false, false };
unsigned int maxvcpus;
+ bool hasSCSI = false;
if (ctx->formatFileName == NULL) {
virReportError(VIR_ERR_INTERNAL_ERROR, "%s",
for (i = 0; i < 4; ++i) {
if (scsi_present[i]) {
+ hasSCSI = true;
+
virBufferAsprintf(&buffer, "scsi%zu.present = \"true\"\n", i);
if (scsi_virtualDev[i] != -1) {
goto cleanup;
}
+ if (virtualHW_version >= 7 && hasSCSI) {
+ virBufferAddLit(&buffer, "pciBridge0.present = \"true\"\n");
+
+ virBufferAddLit(&buffer, "pciBridge4.present = \"true\"\n");
+ virBufferAddLit(&buffer, "pciBridge4.virtualDev = \"pcieRootPort\"\n");
+ virBufferAddLit(&buffer, "pciBridge4.functions = \"8\"\n");
+
+ virBufferAddLit(&buffer, "pciBridge5.present = \"true\"\n");
+ virBufferAddLit(&buffer, "pciBridge5.virtualDev = \"pcieRootPort\"\n");
+ virBufferAddLit(&buffer, "pciBridge5.functions = \"8\"\n");
+
+ virBufferAddLit(&buffer, "pciBridge6.present = \"true\"\n");
+ virBufferAddLit(&buffer, "pciBridge6.virtualDev = \"pcieRootPort\"\n");
+ virBufferAddLit(&buffer, "pciBridge6.functions = \"8\"\n");
+
+ virBufferAddLit(&buffer, "pciBridge7.present = \"true\"\n");
+ virBufferAddLit(&buffer, "pciBridge7.virtualDev = \"pcieRootPort\"\n");
+ virBufferAddLit(&buffer, "pciBridge7.functions = \"8\"\n");
+ }
+
/* Get final VMX output */
if (virBufferCheckError(&buffer) < 0)
goto cleanup;
ethernet1.generatedAddress = "00:0c:29:3b:64:f4"
ethernet1.generatedAddressOffset = "0"
svga.vramSize = "4194304"
+pciBridge0.present = "true"
+pciBridge4.present = "true"
+pciBridge4.virtualDev = "pcieRootPort"
+pciBridge4.functions = "8"
+pciBridge5.present = "true"
+pciBridge5.virtualDev = "pcieRootPort"
+pciBridge5.functions = "8"
+pciBridge6.present = "true"
+pciBridge6.virtualDev = "pcieRootPort"
+pciBridge6.functions = "8"
+pciBridge7.present = "true"
+pciBridge7.virtualDev = "pcieRootPort"
+pciBridge7.functions = "8"
ethernet0.address = "00:90:b9:dc:ea:81"
ethernet0.checkMACAddress = "false"
svga.vramSize = "4194304"
+pciBridge0.present = "true"
+pciBridge4.present = "true"
+pciBridge4.virtualDev = "pcieRootPort"
+pciBridge4.functions = "8"
+pciBridge5.present = "true"
+pciBridge5.virtualDev = "pcieRootPort"
+pciBridge5.functions = "8"
+pciBridge6.present = "true"
+pciBridge6.virtualDev = "pcieRootPort"
+pciBridge6.functions = "8"
+pciBridge7.present = "true"
+pciBridge7.virtualDev = "pcieRootPort"
+pciBridge7.functions = "8"
ethernet0.address = "00:90:b9:dc:ea:81"
ethernet0.checkMACAddress = "false"
svga.vramSize = "4194304"
+pciBridge0.present = "true"
+pciBridge4.present = "true"
+pciBridge4.virtualDev = "pcieRootPort"
+pciBridge4.functions = "8"
+pciBridge5.present = "true"
+pciBridge5.virtualDev = "pcieRootPort"
+pciBridge5.functions = "8"
+pciBridge6.present = "true"
+pciBridge6.virtualDev = "pcieRootPort"
+pciBridge6.functions = "8"
+pciBridge7.present = "true"
+pciBridge7.virtualDev = "pcieRootPort"
+pciBridge7.functions = "8"