]> xenbits.xensource.com Git - people/aperard/xen-unstable.git/commitdiff
x86/vtx: Remove opencoded MSR_ARCH_CAPS check
authorAndrew Cooper <andrew.cooper3@citrix.com>
Mon, 15 May 2023 15:59:25 +0000 (16:59 +0100)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Tue, 8 Aug 2023 15:02:17 +0000 (16:02 +0100)
MSR_ARCH_CAPS data is now included in featureset information.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
(cherry picked from commit 8f6bc7f9b72eb7cf0c8c5ae5d80498a58ba0b7c3)

xen/arch/x86/hvm/vmx/vmx.c
xen/arch/x86/include/asm/cpufeature.h

index 8da6be33eeec7281b87ee742a5c2fd0e6e7dd099..f256dc2635f5f3d43d8474241aaf063c88e4e15c 100644 (file)
@@ -2808,8 +2808,6 @@ static void __init ler_to_fixup_check(void);
  */
 static bool __init has_if_pschange_mc(void)
 {
-    uint64_t caps = 0;
-
     /*
      * If we are virtualised, there is nothing we can do.  Our EPT tables are
      * shadowed by our hypervisor, and not walked by hardware.
@@ -2817,10 +2815,8 @@ static bool __init has_if_pschange_mc(void)
     if ( cpu_has_hypervisor )
         return false;
 
-    if ( cpu_has_arch_caps )
-        rdmsrl(MSR_ARCH_CAPABILITIES, caps);
-
-    if ( caps & ARCH_CAPS_IF_PSCHANGE_MC_NO )
+    /* Hardware reports itself as fixed. */
+    if ( cpu_has_if_pschange_mc_no )
         return false;
 
     /*
index a3ad9ebee4e9ab288da703b36d61cb5c2c123ef2..448d5c1e0560518c6e1b4bd1ea7c97a7c8da23f0 100644 (file)
 #define cpu_has_avx_vnni        boot_cpu_has(X86_FEATURE_AVX_VNNI)
 #define cpu_has_avx512_bf16     boot_cpu_has(X86_FEATURE_AVX512_BF16)
 
+/* MSR_ARCH_CAPS */
+#define cpu_has_if_pschange_mc_no boot_cpu_has(X86_FEATURE_IF_PSCHANGE_MC_NO)
+
 /* Synthesized. */
 #define cpu_has_arch_perfmon    boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
 #define cpu_has_cpuid_faulting  boot_cpu_has(X86_FEATURE_CPUID_FAULTING)