d->arch.evtchn_irq);
/* Set the value of domain param HVM_PARAM_CALLBACK_IRQ */
- val = (u64)HVM_PARAM_CALLBACK_TYPE_PPI << 56;
- val |= (2 << 8); /* Active-low level-sensitive */
- val |= d->arch.evtchn_irq & 0xff;
+ val = MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI,
+ HVM_PARAM_CALLBACK_IRQ_TYPE_MASK);
+ /* Active-low level-sensitive */
+ val |= MASK_INSR(HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL,
+ HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_MASK);
+ val |= d->arch.evtchn_irq;
d->arch.hvm_domain.params[HVM_PARAM_CALLBACK_IRQ] = val;
/*
unsigned int gsi=0, pdev=0, pintx=0;
uint8_t via_type;
- via_type = (uint8_t)(via >> 56) + 1;
+ via_type = (uint8_t)MASK_EXTR(via, HVM_PARAM_CALLBACK_IRQ_TYPE_MASK) + 1;
if ( ((via_type == HVMIRQ_callback_gsi) && (via == 0)) ||
(via_type > HVMIRQ_callback_vector) )
via_type = HVMIRQ_callback_none;
*/
#define HVM_PARAM_CALLBACK_IRQ 0
+#define HVM_PARAM_CALLBACK_IRQ_TYPE_MASK xen_mk_ullong(0xFF00000000000000)
/*
* How should CPU0 event-channel notifications be delivered?
*
* This is only used by ARM/ARM64 and masking/eoi the interrupt associated to
* the notification is handled by the interrupt controller.
*/
+#define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_MASK 0xFF00
+#define HVM_PARAM_CALLBACK_TYPE_PPI_FLAG_LOW_LEVEL 2
#endif
/*