void *pde = NULL;
void *table_vaddr;
u64 next_table_maddr = 0;
+ unsigned int lowest = 1;
- BUG_ON( table == NULL || level == 0 );
+ BUG_ON( table == NULL || level < lowest );
- while ( level > 1 )
+ if ( level == lowest )
+ return page_to_maddr(table);
+
+ while ( level > lowest )
{
offset = io_pfn >> ((PTE_PER_TABLE_SHIFT *
(level - IOMMU_PAGING_MODE_LEVEL_1)));
{
int level = 1;
- BUG_ON(!max_page);
-
- if ( entries > max_page )
- entries = max_page;
+ BUG_ON( !entries );
while ( entries > PTE_PER_TABLE_SIZE )
{
struct pci_dev *pdev;
struct amd_iommu *iommu;
int bdf;
+ struct hvm_iommu *t = domain_hvm_iommu(target);
ASSERT(spin_is_locked(&pcidevs_lock));
pdev = pci_get_pdev_by_domain(source, bus, devfn);
list_move(&pdev->domain_list, &target->arch.pdev_list);
pdev->domain = target;
+ if ( target->max_pages > 0 )
+ t->paging_mode = get_paging_mode(target->max_pages);
+
amd_iommu_setup_domain_device(target, iommu, bdf);
AMD_IOMMU_DEBUG("Re-assign %02x:%02x.%x from domain %d to domain %d\n",
bus, PCI_SLOT(devfn), PCI_FUNC(devfn),