AMD/iommu: SR56x0 Erratum 64 - Reset all head & tail pointers

Reference at time of patch:
http://support.amd.com/us/ChipsetMotherboard_TechDocs/46303.pdf

Erratum 64 states that the head and tail pointers for the Command buffer and
Event log are only reset on a cold boot, not a warm boot.

While the erratum is limited to systems using SR56xx chipsets (such as Family
10h CPUs), resetting the pointers is a sensible action in all cases, including
the PPR log for consistency.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Keir Fraser <keir@xen.org>
Acked-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
master commit: 6d243308e1d75f866679db226159c797d6c83aad
master date: 2013-05-22 15:26:52 +0200

diff --git a/xen/drivers/passthrough/amd/iommu_init.c b/xen/drivers/passthrough/amd/iommu_init.c
index fcb7e87f5fa11fc0a9c1e5535bac3ce373ce16af..adf220b3c67d04380a83507bcce2825e89d9815c 100644 (file)
--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -119,6 +119,11 @@ static void register_iommu_cmd_buffer_in_mmio_space(struct amd_iommu *iommu)
                          IOMMU_CMD_BUFFER_LENGTH_MASK,
                          IOMMU_CMD_BUFFER_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base+IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET);
+
+    /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
+     * automatically for us. */
+    writel(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
+    writel(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
 }
 
 static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu)
@@ -146,6 +151,11 @@ static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu)
                         IOMMU_EVENT_LOG_LENGTH_MASK,
                         IOMMU_EVENT_LOG_LENGTH_SHIFT, &entry);
     writel(entry, iommu->mmio_base+IOMMU_EVENT_LOG_BASE_HIGH_OFFSET);
+
+    /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
+     * automatically for us. */
+    writel(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
+    writel(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
 }
 
 static void set_iommu_translation_control(struct amd_iommu *iommu,