Fix erraneous fallthrough in MIPS trap implementation, thanks Atsushi Nemoto.

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 64f7d75650a6faeceb8e17d4434d3291e6d32dd9..c9cbc9dadbe07114570468a46f1b6a5141bf4e04 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1276,6 +1276,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
             GEN_LOAD_REG_TN(T1, rt);
             cond = 1;
         }
+        break;
     case OPC_TEQI:
     case OPC_TGEI:
     case OPC_TGEIU: