We are currently using a per-platform quirk to know if the 2 4KB region of
the GIC CPU interface are each aligned to 64KB. Although, it may be
possible to have different layout on a same platform (depending on the
firmware version).
Rather than having a quirk it's possible to detect by reading the GIC
memory. This patch is based from the Linux commit "irqchip/GIC: Add workaround
for aliased GIC400" [1].
Take the opportunity to clean up the GICv2 of code which was only
required because of the quirk.
Note that none of the platform using the gic-hip04 were actually using
the quirk, so the code has been dropped. I will let the maintainers
decide whether it's relevant or not to add proper detection for aliased
GIC for this hardware.
[1] commit
12e14066f4835f5ee1ca795f0309415b54c067a9
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Sun Sep 13 12:14:31 2015 +0100
irqchip/GIC: Add workaround for aliased GIC400
The GICv2 architecture mandates that the two 4kB GIC regions are
contiguous, and on two separate physical pages (so that access to
the second page can be trapped by a hypervisor). This doesn't work
very well when PAGE_SIZE is 64kB.
A relatively common hack^Wway to work around this is to alias each
4kB region over its own 64kB page. Of course in this case, the base
address you want to use is not really the begining of the region,
but base + 60kB (so that you get a contiguous 8kB region over two
distinct pages).
Normally, this would be described in DT with a new property, but
some HW is already out there, and the firmware makes sure that
it will override whatever you put in the GIC node. Duh. And of course,
said firmware source code is not available, despite being based
on u-boot.
The workaround is to detect the case where the CPU interface size
is set to 128kB, and verify the aliasing by checking that the ID
register for GIC400 (which is the only GIC wired this way so far)
is the same at base and base + 0xF000. In this case, we update
the GIC base address and let it roll.
And if you feel slightly sick by looking at this, rest assured that
I do too...
Reported-by: Julien Grall <julien.grall@citrix.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Stuart Yoder <stuart.yoder@freescale.com>
Cc: Pavel Fedin <p.fedin@samsung.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1442142873-20213-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Julien Grall <julien.grall@citrix.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
static int __init hip04gic_init(void)
{
int res;
- paddr_t hbase, dbase, cbase, vbase;
+ paddr_t hbase, dbase, cbase, csize, vbase;
const struct dt_device_node *node = gicv2_info.node;
res = dt_device_get_address(node, 0, &dbase, NULL);
if ( res )
panic("GIC-HIP04: Cannot find a valid address for the distributor");
- res = dt_device_get_address(node, 1, &cbase, NULL);
+ res = dt_device_get_address(node, 1, &cbase, &csize);
if ( res )
panic("GIC-HIP04: Cannot find a valid address for the CPU");
panic("GIC-HIP04: Failed to ioremap for GIC distributor\n");
gicv2.map_cbase[0] = ioremap_nocache(cbase, PAGE_SIZE);
-
- if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- gicv2.map_cbase[1] = ioremap_nocache(cbase + SZ_64K, PAGE_SIZE);
- else
- gicv2.map_cbase[1] = ioremap_nocache(cbase + PAGE_SIZE, PAGE_SIZE);
+ gicv2.map_cbase[1] = ioremap_nocache(cbase + PAGE_SIZE, PAGE_SIZE);
if ( !gicv2.map_cbase[0] || !gicv2.map_cbase[1] )
panic("GIC-HIP04: Failed to ioremap for GIC CPU interface\n");
if ( !gicv2.map_hbase )
panic("GIC-HIP04: Failed to ioremap for GIC Virtual interface\n");
- vgic_v2_setup_hw(dbase, cbase, vbase);
+ vgic_v2_setup_hw(dbase, cbase, csize, vbase, 0);
/* Global settings: interrupt distributor */
spin_lock_init(&gicv2.lock);
/* Global state */
static struct {
void __iomem * map_dbase; /* IO mapped Address of distributor registers */
- void __iomem * map_cbase[2]; /* IO mapped Address of CPU interface registers */
+ void __iomem * map_cbase; /* IO mapped Address of CPU interface registers */
void __iomem * map_hbase; /* IO Address of virtual interface registers */
spinlock_t lock;
} gicv2;
static inline void writel_gicc(uint32_t val, unsigned int offset)
{
- unsigned int page = offset >> PAGE_SHIFT;
- offset &= ~PAGE_MASK;
- writel_relaxed(val, gicv2.map_cbase[page] + offset);
+ writel_relaxed(val, gicv2.map_cbase + offset);
}
static inline uint32_t readl_gicc(unsigned int offset)
{
- unsigned int page = offset >> PAGE_SHIFT;
- offset &= ~PAGE_MASK;
- return readl_relaxed(gicv2.map_cbase[page] + offset);
+ return readl_relaxed(gicv2.map_cbase + offset);
}
static inline void writel_gich(uint32_t val, unsigned int offset)
.set_affinity = gicv2_irq_set_affinity,
};
+static bool_t gicv2_is_aliased(paddr_t cbase, paddr_t csize)
+{
+ uint32_t val_low, val_high;
+
+ if ( csize != SZ_128K )
+ return false;
+
+ /*
+ * Verify that we have the first 4kB of a GIC400
+ * aliased over the first 64kB by checking the
+ * GICC_IIDR register on both ends.
+ */
+ val_low = readl_gicc(GICC_IIDR);
+ val_high = readl_gicc(GICC_IIDR + 0xf000);
+
+ return ((val_low & 0xfff0fff) == 0x0202043B && val_low == val_high);
+}
+
static int __init gicv2_init(void)
{
int res;
paddr_t hbase, dbase;
paddr_t cbase, csize;
paddr_t vbase, vsize;
+ uint32_t aliased_offset = 0;
const struct dt_device_node *node = gicv2_info.node;
res = dt_device_get_address(node, 0, &dbase, NULL);
if ( !gicv2.map_dbase )
panic("GICv2: Failed to ioremap for GIC distributor\n");
- gicv2.map_cbase[0] = ioremap_nocache(cbase, PAGE_SIZE);
-
- if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- gicv2.map_cbase[1] = ioremap_nocache(cbase + SZ_64K, PAGE_SIZE);
- else
- gicv2.map_cbase[1] = ioremap_nocache(cbase + PAGE_SIZE, PAGE_SIZE);
-
- if ( !gicv2.map_cbase[0] || !gicv2.map_cbase[1] )
+ gicv2.map_cbase = ioremap_nocache(cbase, csize);
+ if ( !gicv2.map_cbase )
panic("GICv2: Failed to ioremap for GIC CPU interface\n");
+ if ( gicv2_is_aliased(cbase, csize) )
+ {
+ /*
+ * Move the base up by 60kB, so that we have a 8kB contiguous
+ * region, which allows us to use GICC_DIR at its
+ * normal offset.
+ * Note the variable cbase is not updated as we need the original
+ * value for the vGICv2 emulation.
+ */
+ aliased_offset = 0xf000;
+
+ gicv2.map_cbase += aliased_offset;
+
+ printk(XENLOG_WARNING
+ "GICv2: Adjusting CPU interface base to %#"PRIx64"\n",
+ cbase + aliased_offset);
+ }
+
gicv2.map_hbase = ioremap_nocache(hbase, PAGE_SIZE);
if ( !gicv2.map_hbase )
panic("GICv2: Failed to ioremap for GIC Virtual interface\n");
- vgic_v2_setup_hw(dbase, cbase, vbase);
+ vgic_v2_setup_hw(dbase, cbase, csize, vbase, aliased_offset);
/* Global settings: interrupt distributor */
spin_lock_init(&gicv2.lock);
paddr_t dbase)
{
int res;
- paddr_t cbase;
+ paddr_t cbase, csize;
paddr_t vbase, vsize;
/*
* provided.
*/
res = dt_device_get_address(node, 1 + gicv3.rdist_count,
- &cbase, NULL);
+ &cbase, &csize);
if ( res )
return;
printk("GICv3 compatible with GICv2 cbase %#"PRIpaddr" vbase %#"PRIpaddr"\n",
cbase, vbase);
- vgic_v2_setup_hw(dbase, cbase, vbase);
+ vgic_v2_setup_hw(dbase, cbase, csize, vbase, 0);
}
/* Set up the GIC */
"Please upgrade your firmware to the latest version");
}
-static uint32_t xgene_storm_quirks(void)
-{
- return PLATFORM_QUIRK_GIC_64K_STRIDE;
-}
-
static void xgene_storm_reset(void)
{
void __iomem *addr;
.compatible = xgene_storm_dt_compat,
.init = xgene_storm_init,
.reset = xgene_storm_reset,
- .quirks = xgene_storm_quirks,
PLATFORM_END
/*
bool_t enabled;
/* Distributor interface address */
paddr_t dbase;
- /* CPU interface address */
+ /* CPU interface address & size */
paddr_t cbase;
+ paddr_t csize;
/* Virtual CPU interface address */
paddr_t vbase;
+
+ /* Offset to add to get an 8kB contiguous region if GIC is aliased */
+ uint32_t aliased_offset;
} vgic_v2_hw;
-void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t vbase)
+void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
+ paddr_t vbase, uint32_t aliased_offset)
{
vgic_v2_hw.enabled = 1;
vgic_v2_hw.dbase = dbase;
vgic_v2_hw.cbase = cbase;
+ vgic_v2_hw.csize = csize;
vgic_v2_hw.vbase = vbase;
+ vgic_v2_hw.aliased_offset = aliased_offset;
}
static int vgic_v2_distr_mmio_read(struct vcpu *v, mmio_info_t *info,
static int vgic_v2_domain_init(struct domain *d)
{
int i, ret;
- paddr_t cbase;
+ paddr_t cbase, csize;
+ paddr_t vbase;
/*
* The hardware domain gets the hardware address.
if ( is_hardware_domain(d) )
{
d->arch.vgic.dbase = vgic_v2_hw.dbase;
+ /*
+ * For the hardware domain, we always map the whole HW CPU
+ * interface region in order to match the device tree (the "reg"
+ * properties is copied as it is).
+ * Note that we assume the size of the CPU interface is always
+ * aligned to PAGE_SIZE.
+ */
cbase = vgic_v2_hw.cbase;
+ csize = vgic_v2_hw.csize;
+ vbase = vgic_v2_hw.vbase;
}
else
{
d->arch.vgic.dbase = GUEST_GICD_BASE;
+ /*
+ * The CPU interface exposed to the guest is always 8kB. We may
+ * need to add an offset to the virtual CPU interface base
+ * address when in the GIC is aliased to get a 8kB contiguous
+ * region.
+ */
+ BUILD_BUG_ON(GUEST_GICC_SIZE != SZ_8K);
cbase = GUEST_GICC_BASE;
+ csize = GUEST_GICC_SIZE;
+ vbase = vgic_v2_hw.vbase + vgic_v2_hw.aliased_offset;
}
/*
* Map the gic virtual cpu interface in the gic cpu interface
* region of the guest.
- *
- * The second page is always mapped at +4K irrespective of the
- * GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
*/
- ret = map_mmio_regions(d, paddr_to_pfn(cbase), 1,
- paddr_to_pfn(vgic_v2_hw.vbase));
- if ( ret )
- return ret;
-
- if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
- ret = map_mmio_regions(d, paddr_to_pfn(cbase + PAGE_SIZE),
- 1, paddr_to_pfn(vgic_v2_hw.vbase + PAGE_SIZE));
- else
- ret = map_mmio_regions(d, paddr_to_pfn(cbase + PAGE_SIZE),
- 1, paddr_to_pfn(vgic_v2_hw.vbase + SZ_64K));
-
+ ret = map_mmio_regions(d, paddr_to_pfn(cbase), csize / PAGE_SIZE,
+ paddr_to_pfn(vbase));
if ( ret )
return ret;
#define GICC_HPPIR (0x0018)
#define GICC_APR (0x00D0)
#define GICC_NSAPR (0x00E0)
+#define GICC_IIDR (0x00FC)
#define GICC_DIR (0x1000)
#define GICH_HCR (0x00)
const struct dt_device_match *blacklist_dev;
};
-/*
- * Quirk for platforms where the 4K GIC register ranges are placed at
- * 64K stride.
- */
-#define PLATFORM_QUIRK_GIC_64K_STRIDE (1 << 0)
-
void __init platform_init(void);
int __init platform_init_time(void);
int __init platform_specific_mapping(struct domain *d);
extern void vgic_free_virq(struct domain *d, unsigned int virq);
-void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t vbase);
+void vgic_v2_setup_hw(paddr_t dbase, paddr_t cbase, paddr_t csize,
+ paddr_t vbase, uint32_t aliased_offset);
#ifdef HAS_GICV3
struct rdist_region;
projects / people / julieng / xen-unstable.git / commitdiff