if (s) {
DisplayState *ds = s->ds;
active_console = s;
- ds->surface = qemu_resize_displaysurface(ds->surface, s->g_width,
- s->g_height, 32, 4 * s->g_width);
+ if (ds_get_bits_per_pixel(s->ds)) {
+ ds->surface = qemu_resize_displaysurface(ds->surface, s->g_width,
+ s->g_height, 32, 4 * s->g_width);
+ } else {
+ s->ds->surface->width = s->width;
+ s->ds->surface->height = s->height;
+ }
dpy_resize(s->ds);
vga_hw_invalidate();
}
static void text_console_invalidate(void *opaque)
{
TextConsole *s = (TextConsole *) opaque;
-
+ if (!ds_get_bits_per_pixel(s->ds) && s->console_type == TEXT_CONSOLE) {
+ s->g_width = ds_get_width(s->ds);
+ s->g_height = ds_get_height(s->ds);
+ text_console_resize(s);
+ }
console_refresh(s);
}
}
}
+static TextConsole *get_graphic_console(DisplayState *ds)
+{
+ int i;
+ TextConsole *s;
+ for (i = 0; i < nb_consoles; i++) {
+ s = consoles[i];
+ if (s->console_type == GRAPHIC_CONSOLE && s->ds == ds)
+ return s;
+ }
+ return NULL;
+}
+
static TextConsole *new_console(DisplayState *ds, console_type_t console_type)
{
TextConsole *s;
consoles[i] = consoles[i - 1];
}
consoles[i] = s;
+ nb_consoles++;
}
return s;
}
-TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
- vga_hw_invalidate_ptr invalidate,
- vga_hw_screen_dump_ptr screen_dump,
- vga_hw_text_update_ptr text_update,
- void *opaque)
+DisplayState *graphic_console_init(vga_hw_update_ptr update,
+ vga_hw_invalidate_ptr invalidate,
+ vga_hw_screen_dump_ptr screen_dump,
+ vga_hw_text_update_ptr text_update,
+ void *opaque)
{
TextConsole *s;
+ DisplayState *ds;
+
+ ds = (DisplayState *) qemu_mallocz(sizeof(DisplayState));
+ if (ds == NULL)
+ return NULL;
+ ds->surface = qemu_create_displaysurface(640, 480, 32, 640 * 4);
s = new_console(ds, GRAPHIC_CONSOLE);
- if (!s)
- return NULL;
+ if (s == NULL) {
+ qemu_free_displaysurface(ds->surface);
+ qemu_free(ds);
+ return NULL;
+ }
s->hw_update = update;
s->hw_invalidate = invalidate;
s->hw_screen_dump = screen_dump;
s->hw_text_update = text_update;
s->hw = opaque;
- return s;
+
+ register_displaystate(ds);
+ return ds;
}
int is_graphic_console(void)
}
}
-CharDriverState *text_console_init(DisplayState *ds, const char *p)
+static int n_text_consoles;
+static CharDriverState *text_consoles[128];
+static char *text_console_strs[128];
+
+static void text_console_do_init(CharDriverState *chr, DisplayState *ds, const char *p)
{
- CharDriverState *chr;
TextConsole *s;
static int color_inited;
- chr = qemu_mallocz(sizeof(CharDriverState));
- if (!chr)
- return NULL;
s = new_console(ds, (p == 0) ? TEXT_CONSOLE : TEXT_CONSOLE_FIXED_SIZE);
if (!s) {
free(chr);
- return NULL;
+ return;
}
chr->opaque = s;
chr->chr_write = console_puts;
s->out_fifo.buf = s->out_fifo_buf;
s->out_fifo.buf_size = sizeof(s->out_fifo_buf);
s->kbd_timer = qemu_new_timer(rt_clock, kbd_send_chars, s);
+ s->ds = ds;
if (!color_inited) {
color_inited = 1;
text_console_resize(s);
qemu_chr_reset(chr);
+}
+
+CharDriverState *text_console_init(const char *p)
+{
+ CharDriverState *chr;
+
+ chr = qemu_mallocz(sizeof(CharDriverState));
+ if (!chr)
+ return NULL;
+
+ if (n_text_consoles == 128) {
+ fprintf(stderr, "Too many text consoles\n");
+ exit(1);
+ }
+ text_consoles[n_text_consoles] = chr;
+ text_console_strs[n_text_consoles] = p ? qemu_strdup(p) : NULL;
+ n_text_consoles++;
return chr;
}
-void qemu_console_resize(QEMUConsole *console, int width, int height)
+void text_consoles_set_display(DisplayState *ds)
{
- console->g_width = width;
- console->g_height = height;
- if (active_console == console) {
- DisplayState *ds = console->ds;
+ int i;
+
+ for (i = 0; i < n_text_consoles; i++) {
+ text_console_do_init(text_consoles[i], ds, text_console_strs[i]);
+ qemu_free(text_console_strs[i]);
+ }
+
+ n_text_consoles = 0;
+}
+
+void qemu_console_resize(DisplayState *ds, int width, int height)
+{
+ TextConsole *s = get_graphic_console(ds);
+ if (!s) return;
+ s->g_width = width;
+ s->g_height = height;
+ if (is_graphic_console()) {
ds->surface = qemu_resize_displaysurface(ds->surface, width, height, 32, 4 * width);
- dpy_resize(console->ds);
+ dpy_resize(ds);
}
}
-void qemu_console_copy(QEMUConsole *console, int src_x, int src_y,
+void qemu_console_copy(DisplayState *ds, int src_x, int src_y,
int dst_x, int dst_y, int w, int h)
{
- if (active_console == console)
- dpy_copy(console->ds, src_x, src_y, dst_x, dst_y, w, h);
+ if (is_graphic_console()) {
+ dpy_copy(ds, src_x, src_y, dst_x, dst_y, w, h);
+ }
}
PixelFormat qemu_different_endianness_pixelformat(int bpp)
void (*mouse_set)(int x, int y, int on);
void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
uint8_t *image, uint8_t *mask);
+
+ struct DisplayState *next;
};
+void register_displaystate(DisplayState *ds);
+DisplayState *get_displaystate(void);
DisplaySurface* qemu_create_displaysurface(int width, int height, int bpp, int linesize);
DisplaySurface* qemu_resize_displaysurface(DisplaySurface *surface,
int width, int height, int bpp, int linesize);
typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
typedef void (*vga_hw_text_update_ptr)(void *, console_ch_t *);
-TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
+DisplayState *graphic_console_init(vga_hw_update_ptr update,
vga_hw_invalidate_ptr invalidate,
vga_hw_screen_dump_ptr screen_dump,
vga_hw_text_update_ptr text_update,
int is_graphic_console(void);
int is_fixedsize_console(void);
-CharDriverState *text_console_init(DisplayState *ds, const char *p);
+CharDriverState *text_console_init(const char *p);
+void text_consoles_set_display(DisplayState *ds);
void console_select(unsigned int index);
void console_color_init(DisplayState *ds);
-void qemu_console_resize(QEMUConsole *console, int width, int height);
-void qemu_console_copy(QEMUConsole *console, int src_x, int src_y,
+void qemu_console_resize(DisplayState *ds, int width, int height);
+void qemu_console_copy(DisplayState *ds, int src_x, int src_y,
int dst_x, int dst_y, int w, int h);
/* sdl.c */
gheight = ds_get_height(ds);
curses_calc_pad();
+ ds->surface->width = width * FONT_WIDTH;
+ ds->surface->height = height * FONT_HEIGHT;
}
#ifndef _WIN32
dcl->dpy_text_cursor = curses_cursor_position;
register_displaychangelistener(ds, dcl);
qemu_free_displaysurface(ds->surface);
- ds->surface = qemu_create_displaysurface_from(80, 25, 0, 0, (uint8_t*) screen);
+ ds->surface = qemu_create_displaysurface_from(640, 400, 0, 0, (uint8_t*) screen);
invalidate = 1;
/* Board init. */
static void an5206_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
uint8_t iformat;
uint8_t source;
DisplayState *state;
- QEMUConsole *console;
blizzard_fn_t *line_fn_tab[2];
void *fb;
if (s->x != ds_get_width(s->state) || s->y != ds_get_height(s->state)) {
s->invalidate = 1;
- qemu_console_resize(s->console, s->x, s->y);
+ qemu_console_resize(s->state, s->x, s->y);
}
if (s->invalidate) {
#define DEPTH 32
#include "blizzard_template.h"
-void *s1d13745_init(qemu_irq gpio_int, DisplayState *ds)
+void *s1d13745_init(qemu_irq gpio_int)
{
struct blizzard_s *s = (struct blizzard_s *) qemu_mallocz(sizeof(*s));
- s->state = ds;
s->fb = qemu_malloc(0x180000);
switch (ds_get_bits_per_pixel(s->state)) {
blizzard_reset(s);
- s->console = graphic_console_init(s->state, blizzard_update_display,
- blizzard_invalidate_display,
- blizzard_screen_dump, NULL, s);
+ s->state = graphic_console_init(blizzard_update_display,
+ blizzard_invalidate_display,
+ blizzard_screen_dump, NULL, s);
return s;
}
#define HW_BOARDS_H
typedef void QEMUMachineInitFunc(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
s->cirrus_blt_width, s->cirrus_blt_height);
if (notify)
- qemu_console_copy(s->console,
+ qemu_console_copy(s->ds,
sx, sy, dx, dy,
s->cirrus_blt_width / depth,
s->cirrus_blt_height);
*
***************************************/
-void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
+void isa_cirrus_vga_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
CirrusVGAState *s;
}
vga_common_init((VGAState *)s,
- ds, vga_ram_base, vga_ram_offset, vga_ram_size);
+ vga_ram_base, vga_ram_offset, vga_ram_size);
cirrus_init_common(s, CIRRUS_ID_CLGD5430, 0);
/* XXX ISA-LFB support */
}
s->cirrus_mmio_io_addr);
}
-void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
PCICirrusVGAState *d;
vga_ram_size = 4*1024*1024;
}
vga_common_init((VGAState *)s,
- ds, vga_ram_base, vga_ram_offset, vga_ram_size);
+ vga_ram_base, vga_ram_offset, vga_ram_size);
cirrus_init_common(s, device_id, 1);
+
s->pci_dev = (PCIDevice *)d;
/* setup memory space */
/* ssd0323.c */
int ssd0323_xfer_ssi(void *opaque, int data);
-void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p);
+void *ssd0323_init(qemu_irq *cmd_p);
/* ads7846.c */
struct ads7846_state_s;
void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode);
/* blizzard.c */
-void *s1d13745_init(qemu_irq gpio_int, DisplayState *ds);
+void *s1d13745_init(qemu_irq gpio_int);
void s1d13745_write(void *opaque, int dc, uint16_t value);
void s1d13745_write_block(void *opaque, int dc,
void *buf, size_t len, int pitch);
/* Board init. */
static void dummy_m68k_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
static
void bareetraxfs_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
uint8_t palette[256][3];
/* display refresh support */
DisplayState *ds;
- QEMUConsole *console;
int graphic_mode;
uint32_t scr_width, scr_height; /* in pixels */
} G364State;
full_update = 1;
}
if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
- qemu_console_resize(s->console, s->scr_width, s->scr_height);
+ qemu_console_resize(s->ds, s->scr_width, s->scr_height);
full_update = 1;
}
switch(graphic_mode) {
g364fb_mem_writel,
};
-int g364fb_mm_init(DisplayState *ds,
- int vram_size, int it_shift,
+int g364fb_mm_init(int vram_size, int it_shift,
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base)
{
G364State *s;
qemu_register_reset(g364fb_reset, s);
g364fb_reset(s);
- s->ds = ds;
s->vram_base = vram_base;
- s->console = graphic_console_init(ds, g364fb_update_display,
- g364fb_invalidate_display,
- g364fb_screen_dump, NULL, s);
+ s->ds = graphic_console_init(g364fb_update_display,
+ g364fb_invalidate_display,
+ g364fb_screen_dump, NULL, s);
io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
cpu_register_physical_memory(s->vram_base, vram_size, io_vram);
static const int sector_len = 128 * 1024;
static void connex_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
exit(1);
}
- cpu = pxa255_init(connex_ram, ds);
+ cpu = pxa255_init(connex_ram);
index = drive_get_index(IF_PFLASH, 0, 0);
if (index == -1) {
}
static void verdex_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
exit(1);
}
- cpu = pxa270_init(verdex_ram, ds, cpu_model ?: "pxa270-c0");
+ cpu = pxa270_init(verdex_ram, cpu_model ?: "pxa270-c0");
index = drive_get_index(IF_PFLASH, 0, 0);
if (index == -1) {
void wm8750_set_bclk_in(void *opaque, int hz);
/* ssd0303.c */
-void ssd0303_init(DisplayState *ds, i2c_bus *bus, int address);
+void ssd0303_init(i2c_bus *bus, int address);
/* twl92230.c */
i2c_slave *twl92230_init(i2c_bus *bus, qemu_irq irq);
};
static void integratorcp_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
exit (1);
}
}
- pl110_init(ds, 0xc0000000, pic[22], 0);
+ pl110_init(0xc0000000, pic[22], 0);
integrator_binfo.ram_size = ram_size;
integrator_binfo.kernel_filename = kernel_filename;
target_phys_addr_t base;
uint8_t segments;
DisplayState *ds;
- QEMUConsole *console;
screen_state_t state;
} LedState;
char buf[2];
dpy_cursor(s->ds, -1, -1);
- qemu_console_resize(s->console, 2, 1);
+ qemu_console_resize(s->ds, 2, 1);
/* TODO: draw the segments */
snprintf(buf, 2, "%02hhx\n", s->segments);
dpy_update(s->ds, 0, 0, 2, 1);
}
-void jazz_led_init(DisplayState *ds, target_phys_addr_t base)
+void jazz_led_init(target_phys_addr_t base)
{
LedState *s;
int io;
return;
s->base = base;
- s->ds = ds;
s->state = REDRAW_SEGMENTS | REDRAW_BACKGROUND;
io = cpu_register_io_memory(0, led_read, led_write, s);
cpu_register_physical_memory(s->base, 1, io);
- s->console = graphic_console_init(ds, jazz_led_update_display,
- jazz_led_invalidate_display,
- jazz_led_screen_dump,
- jazz_led_text_update, s);
- qemu_console_resize(s->console, 60, 80);
+ s->ds = graphic_console_init(jazz_led_update_display,
+ jazz_led_invalidate_display,
+ jazz_led_screen_dump,
+ jazz_led_text_update, s);
+ qemu_console_resize(s->ds, 60, 80);
}
};
static void mainstone_common_init(ram_addr_t ram_size, int vga_ram_size,
- DisplayState *ds, const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
{
exit(1);
}
- cpu = pxa270_init(mainstone_binfo.ram_size, ds, cpu_model);
+ cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model);
cpu_register_physical_memory(0, MAINSTONE_ROM,
qemu_ram_alloc(MAINSTONE_ROM) | IO_MEM_ROM);
}
static void mainstone_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mainstone_common_init(ram_size, vga_ram_size, ds, kernel_filename,
+ mainstone_common_init(ram_size, vga_ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
}
}
static void mcf5208evb_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
void ds1225y_set_protection(void *opaque, int protection);
/* g364fb.c */
-int g364fb_mm_init(DisplayState *ds,
- int vram_size, int it_shift,
+int g364fb_mm_init(int vram_size, int it_shift,
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base);
/* mipsnet.c */
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
/* jazz_led.c */
-extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
+extern void jazz_led_init(target_phys_addr_t base);
/* mips_int.c */
extern void cpu_mips_irq_init_cpu(CPUState *env);
static
void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
- DisplayState *ds, const char *cpu_model,
+ const char *cpu_model,
enum jazz_model_e jazz_model)
{
char buf[1024];
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
- g364fb_mm_init(ds, vga_ram_size, 0, 0x40000000, 0x60000000);
+ g364fb_mm_init(vga_ram_size, 0, 0x40000000, 0x60000000);
break;
case JAZZ_PICA61:
- isa_vga_mm_init(ds, phys_ram_base + ram_size, ram_size, vga_ram_size,
+ isa_vga_mm_init(phys_ram_base + ram_size, ram_size, vga_ram_size,
0x40000000, 0x60000000, 0);
break;
default:
ds1225y_init(0x80009000, "nvram");
/* LED indicator */
- jazz_led_init(ds, 0x8000f000);
+ jazz_led_init(0x8000f000);
}
static
void mips_magnum_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mips_jazz_init(ram_size, vga_ram_size, ds, cpu_model, JAZZ_MAGNUM);
+ mips_jazz_init(ram_size, vga_ram_size, cpu_model, JAZZ_MAGNUM);
}
static
void mips_pica61_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- mips_jazz_init(ram_size, vga_ram_size, ds, cpu_model, JAZZ_PICA61);
+ mips_jazz_init(ram_size, vga_ram_size, cpu_model, JAZZ_PICA61);
}
QEMUMachine mips_magnum_machine = {
static
void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
network_init(pci_bus);
/* Optional PCI video card */
- pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + ram_size,
+ pci_cirrus_vga_init(pci_bus, phys_ram_base + ram_size,
ram_size, vga_ram_size);
}
static void
mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
static const int sector_len = 32 * 1024;
static
void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
}
}
- isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
+ isa_vga_init(phys_ram_base + ram_size, ram_size,
vga_ram_size);
if (nd_table[0].vlan) {
int page;
int page_off;
DisplayState *ds;
- QEMUConsole *console;
uint8_t video_ram[128*64/8];
} musicpal_lcd_state;
musicpal_lcd_write
};
-static void musicpal_lcd_init(DisplayState *ds, uint32_t base)
+static void musicpal_lcd_init(uint32_t base)
{
musicpal_lcd_state *s;
int iomemtype;
if (!s)
return;
s->base = base;
- s->ds = ds;
iomemtype = cpu_register_io_memory(0, musicpal_lcd_readfn,
musicpal_lcd_writefn, s);
cpu_register_physical_memory(base, MP_LCD_SIZE, iomemtype);
- s->console = graphic_console_init(ds, lcd_refresh, lcd_invalidate,
- NULL, NULL, s);
- qemu_console_resize(s->console, 128*3, 64*3);
+ s->ds = graphic_console_init(lcd_refresh, lcd_invalidate,
+ NULL, NULL, s);
+ qemu_console_resize(s->ds, 128*3, 64*3);
}
/* PIC register offsets */
};
static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
}
mv88w8618_flashcfg_init(MP_FLASHCFG_BASE);
- musicpal_lcd_init(ds, MP_LCD_BASE);
+ musicpal_lcd_init(MP_LCD_BASE);
qemu_add_kbd_event_handler(musicpal_key_event, pic[MP_GPIO_IRQ]);
free(fb_blank);
}
-static void n8x0_dss_setup(struct n800_s *s, DisplayState *ds)
+static void n8x0_dss_setup(struct n800_s *s)
{
- s->blizzard.opaque = s1d13745_init(0, ds);
+ s->blizzard.opaque = s1d13745_init(0);
s->blizzard.block = s1d13745_write_block;
s->blizzard.write = s1d13745_write;
s->blizzard.read = s1d13745_read;
}
static void n8x0_init(ram_addr_t ram_size, const char *boot_device,
- DisplayState *ds, const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, struct arm_boot_info *binfo, int model)
{
struct n800_s *s = (struct n800_s *) qemu_mallocz(sizeof(*s));
int sdram_size = binfo->ram_size;
int onenandram_size = 0x00010000;
+ DisplayState *ds = get_displaystate();
if (ram_size < sdram_size + onenandram_size + OMAP242X_SRAM_SIZE) {
fprintf(stderr, "This architecture uses %i bytes of memory\n",
exit(1);
}
- s->cpu = omap2420_mpu_init(sdram_size, NULL, cpu_model);
+ s->cpu = omap2420_mpu_init(sdram_size, cpu_model);
/* Setup peripherals
*
n810_kbd_setup(s);
}
n8x0_spi_setup(s);
- n8x0_dss_setup(s, ds);
+ n8x0_dss_setup(s);
n8x0_cbus_setup(s);
n8x0_uart_setup(s);
if (usb_enabled)
};
static void n800_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- return n8x0_init(ram_size, boot_device, ds,
+ return n8x0_init(ram_size, boot_device,
kernel_filename, kernel_cmdline, initrd_filename,
cpu_model, &n800_binfo, 800);
}
static void n810_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- return n8x0_init(ram_size, boot_device, ds,
+ return n8x0_init(ram_size, boot_device,
kernel_filename, kernel_cmdline, initrd_filename,
cpu_model, &n810_binfo, 810);
}
struct omap_lcd_panel_s;
void omap_lcdc_reset(struct omap_lcd_panel_s *s);
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
- struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
+ struct omap_dma_lcd_channel_s *dma,
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
/* omap_dss.c */
struct omap_dss_s;
void omap_dss_reset(struct omap_dss_s *s);
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
- target_phys_addr_t l3_base, DisplayState *ds,
+ target_phys_addr_t l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2);
/* omap1.c */
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
- DisplayState *ds, const char *core);
+ const char *core);
/* omap2.c */
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
- DisplayState *ds, const char *core);
+ const char *core);
# if TARGET_PHYS_ADDR_BITS == 32
# define OMAP_FMT_plx "%#08x"
}
struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
- DisplayState *ds, const char *core)
+ const char *core)
{
int i;
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
omap_findclk(s, "clk32-kHz"));
s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
- omap_dma_get_lcdch(s->dma), ds, imif_base, emiff_base,
+ omap_dma_get_lcdch(s->dma), imif_base, emiff_base,
omap_findclk(s, "lcd_ck"));
omap_ulpd_pm_init(0xfffe0800, s);
};
struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
- DisplayState *ds, const char *core)
+ const char *core)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
qemu_mallocz(sizeof(struct omap_mpu_state_s));
omap_findclk(s, "spi2_fclk"),
omap_findclk(s, "spi2_iclk"));
- s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800, ds,
+ s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
/* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
};
struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
- target_phys_addr_t l3_base, DisplayState *ds,
+ target_phys_addr_t l3_base,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
omap_clk ick1, omap_clk ick2)
s->irq = irq;
s->drq = drq;
- s->state = ds;
omap_dss_reset(s);
iomemtype[0] = l4_register_io_memory(0, omap_diss1_readfn,
cpu_register_physical_memory(s->im3_base, 0x1000, iomemtype[4]);
#if 0
- if (ds)
- graphic_console_init(ds, omap_update_display,
- omap_invalidate_display, omap_screen_dump, s);
+ s->state = graphic_console_init(omap_update_display,
+ omap_invalidate_display, omap_screen_dump, s);
#endif
return s;
target_phys_addr_t base;
qemu_irq irq;
DisplayState *state;
- QEMUConsole *console;
ram_addr_t imif_base;
ram_addr_t emiff_base;
width = omap_lcd->width;
if (width != ds_get_width(omap_lcd->state) ||
omap_lcd->height != ds_get_height(omap_lcd->state)) {
- qemu_console_resize(omap_lcd->console,
+ qemu_console_resize(omap_lcd->state,
omap_lcd->width, omap_lcd->height);
omap_lcd->invalidate = 1;
}
}
struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
- struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
+ struct omap_dma_lcd_channel_s *dma,
ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
{
int iomemtype;
s->irq = irq;
s->dma = dma;
s->base = base;
- s->state = ds;
s->imif_base = imif_base;
s->emiff_base = emiff_base;
omap_lcdc_reset(s);
omap_lcdc_writefn, s);
cpu_register_physical_memory(s->base, 0x100, iomemtype);
- s->console = graphic_console_init(ds, omap_update_display,
- omap_invalidate_display,
- omap_screen_dump, NULL, s);
+ s->state = graphic_console_init(omap_update_display,
+ omap_invalidate_display,
+ omap_screen_dump, NULL, s);
return s;
}
};
static void palmte_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
static uint32_t cs3val = 0xe1a0e1a0;
ram_addr_t phys_flash;
int rom_size, rom_loaded = 0;
+ DisplayState *ds = get_displaystate();
if (ram_size < flash_size + sdram_size + OMAP15XX_SRAM_SIZE) {
fprintf(stderr, "This architecture uses %i bytes of memory\n",
exit(1);
}
- cpu = omap310_mpu_init(sdram_size, ds, cpu_model);
+ cpu = omap310_mpu_init(sdram_size, cpu_model);
/* External Flash (EMIFS) */
cpu_register_physical_memory(OMAP_CS0_BASE, flash_size,
/* PC hardware initialisation */
static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename,
int pci_enabled, const char *cpu_model,
if (cirrus_vga_enabled) {
if (pci_enabled) {
pci_cirrus_vga_init(pci_bus,
- ds, phys_ram_base + vga_ram_addr,
+ phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
} else {
- isa_cirrus_vga_init(ds, phys_ram_base + vga_ram_addr,
+ isa_cirrus_vga_init(phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
}
} else if (vmsvga_enabled) {
if (pci_enabled)
- pci_vmsvga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
+ pci_vmsvga_init(pci_bus, phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
else
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
} else {
if (pci_enabled) {
- pci_vga_init(pci_bus, ds, phys_ram_base + vga_ram_addr,
+ pci_vga_init(pci_bus, phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size, 0, 0);
} else {
- isa_vga_init(ds, phys_ram_base + vga_ram_addr,
+ isa_vga_init(phys_ram_base + vga_ram_addr,
vga_ram_addr, vga_ram_size);
}
}
}
static void pc_init_pci(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model,
const char *direct_pci)
{
- pc_init1(ram_size, vga_ram_size, boot_device, ds,
+ pc_init1(ram_size, vga_ram_size, boot_device,
kernel_filename, kernel_cmdline,
initrd_filename, 1, cpu_model,
direct_pci);
}
static void pc_init_isa(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model,
const char *direct_pci)
{
- pc_init1(ram_size, vga_ram_size, boot_device, ds,
+ pc_init1(ram_size, vga_ram_size, boot_device,
kernel_filename, kernel_cmdline,
initrd_filename, 0, cpu_model,
direct_pci);
extern enum vga_retrace_method vga_retrace_method;
-int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
+int isa_vga_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
-int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
unsigned long vga_bios_offset, int vga_bios_size);
-int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
+int isa_vga_mm_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
int it_shift);
/* cirrus_vga.c */
-void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
-void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
+void isa_cirrus_vga_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
/* ide.c */
void *lsi_scsi_init(PCIBus *bus, int devfn);
/* vmware_vga.c */
-void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
/* usb-uhci.c */
typedef struct {
uint32_t base;
DisplayState *ds;
- QEMUConsole *console;
/* The Versatile/PB uses a slightly modified PL110 controller. */
int versatile;
{
if (width != s->cols || height != s->rows) {
if (pl110_enabled(s)) {
- qemu_console_resize(s->console, width, height);
+ qemu_console_resize(s->ds, width, height);
}
}
s->cols = width;
s->cr = val;
s->bpp = (val >> 1) & 7;
if (pl110_enabled(s)) {
- qemu_console_resize(s->console, s->cols, s->rows);
+ qemu_console_resize(s->ds, s->cols, s->rows);
}
break;
case 10: /* LCDICR */
pl110_write
};
-void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq,
- int versatile)
+void *pl110_init(uint32_t base, qemu_irq irq, int versatile)
{
pl110_state *s;
int iomemtype;
pl110_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
s->base = base;
- s->ds = ds;
s->versatile = versatile;
s->irq = irq;
- s->console = graphic_console_init(ds, pl110_update_display,
- pl110_invalidate_display,
- NULL, NULL, s);
+ s->ds = graphic_console_init(pl110_update_display,
+ pl110_invalidate_display,
+ NULL, NULL, s);
/* ??? Save/restore. */
return s;
}
}
static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
}
static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
/* PowerPC Mac99 hardware initialisation */
static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL);
pci_bus = pci_pmac_init(pic);
/* init basic PC hardware */
- pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
+ pci_vga_init(pci_bus, phys_ram_base + ram_size,
ram_size, vga_ram_size,
vga_bios_offset, vga_bios_size);
}
static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
}
pic = heathrow_pic_init(&pic_mem_index, 1, heathrow_irqs);
pci_bus = pci_grackle_init(0xfec00000, pic);
- pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
+ pci_vga_init(pci_bus, phys_ram_base + ram_size,
ram_size, vga_ram_size,
vga_bios_offset, vga_bios_size);
/* PowerPC PREP hardware initialisation */
static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
/* init basic PC hardware */
- pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
+ pci_vga_init(pci_bus, phys_ram_base + ram_size, ram_size,
vga_ram_size, 0, 0);
// openpic = openpic_init(0x00000000, 0xF0000000, 1);
// pit = pit_init(0x40, i8259[0]);
void pl031_init(uint32_t base, qemu_irq irq);
/* pl110.c */
-void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
+void *pl110_init(uint32_t base, qemu_irq irq, int);
/* pl011.c */
enum pl011_type {
/* pxa2xx_lcd.c */
struct pxa2xx_lcdc_s;
struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base,
- qemu_irq irq, DisplayState *ds);
+ qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);
# define PA_FMT "0x%08lx"
# define REG_FMT "0x" TARGET_FMT_plx
-struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, DisplayState *ds,
- const char *revision);
-struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size, DisplayState *ds);
+struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision);
+struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size);
/* usb-ohci.c */
void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
}
/* Initialise a PXA270 integrated chip (ARM based core). */
-struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
- DisplayState *ds, const char *revision)
+struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size, const char *revision)
{
struct pxa2xx_state_s *s;
struct pxa2xx_ssp_s *ssp;
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
s->dma, serial_hds[i]);
- if (ds)
- s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
+ s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
}
/* Initialise a PXA255 integrated chip (ARM based core). */
-struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
- DisplayState *ds)
+struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size)
{
struct pxa2xx_state_s *s;
struct pxa2xx_ssp_s *ssp;
s->fir = pxa2xx_fir_init(0x40800000, s->pic[PXA2XX_PIC_ICP],
s->dma, serial_hds[i]);
- if (ds)
- s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD], ds);
+ s->lcd = pxa2xx_lcdc_init(0x44000000, s->pic[PXA2XX_PIC_LCD]);
s->cm_base = 0x41300000;
s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
int invalidated;
DisplayState *ds;
- QEMUConsole *console;
drawfn *line_fn[2];
int dest_width;
int xres, yres;
if (width != s->xres || height != s->yres) {
if (s->orientation)
- qemu_console_resize(s->console, height, width);
+ qemu_console_resize(s->ds, height, width);
else
- qemu_console_resize(s->console, width, height);
+ qemu_console_resize(s->ds, width, height);
s->invalidated = 1;
s->xres = width;
s->yres = height;
#define BITS 32
#include "pxa2xx_template.h"
-struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq,
- DisplayState *ds)
+struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
{
int iomemtype;
struct pxa2xx_lcdc_s *s;
s->base = base;
s->invalidated = 1;
s->irq = irq;
- s->ds = ds;
pxa2xx_lcdc_orientation(s, graphic_rotate);
pxa2xx_lcdc_writefn, s);
cpu_register_physical_memory(base, 0x00100000, iomemtype);
- s->console = graphic_console_init(ds, pxa2xx_update_display,
- pxa2xx_invalidate_display,
- pxa2xx_screen_dump, NULL, s);
+ s->ds = graphic_console_init(pxa2xx_update_display,
+ pxa2xx_invalidate_display,
+ pxa2xx_screen_dump, NULL, s);
switch (ds_get_bits_per_pixel(s->ds)) {
case 0:
}
static void r2d_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState * ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
};
static void realview_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
sp804_init(0x10011000, pic[4]);
sp804_init(0x10012000, pic[5]);
- pl110_init(ds, 0x10020000, pic[23], 1);
+ pl110_init(0x10020000, pic[23], 1);
index = drive_get_index(IF_SD, 0, 0);
if (index == -1) {
}
static void shix_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState * ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
};
static void spitz_common_init(ram_addr_t ram_size, int vga_ram_size,
- DisplayState *ds, const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum spitz_model_e model, int arm_id)
{
SPITZ_RAM + SPITZ_ROM + PXA2XX_INTERNAL_SIZE);
exit(1);
}
- cpu = pxa270_init(spitz_binfo.ram_size, ds, cpu_model);
+ cpu = pxa270_init(spitz_binfo.ram_size, cpu_model);
sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
}
static void spitz_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
+ spitz_common_init(ram_size, vga_ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9);
}
static void borzoi_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
+ spitz_common_init(ram_size, vga_ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f);
}
static void akita_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
+ spitz_common_init(ram_size, vga_ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8);
}
static void terrier_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- spitz_common_init(ram_size, vga_ram_size, ds, kernel_filename,
+ spitz_common_init(ram_size, vga_ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f);
}
typedef struct {
i2c_slave i2c;
DisplayState *ds;
- QEMUConsole *console;
int row;
int col;
int start_line;
return 0;
}
-void ssd0303_init(DisplayState *ds, i2c_bus *bus, int address)
+void ssd0303_init(i2c_bus *bus, int address)
{
ssd0303_state *s;
s = (ssd0303_state *)i2c_slave_init(bus, address, sizeof(ssd0303_state));
- s->ds = ds;
s->i2c.event = ssd0303_event;
s->i2c.recv = ssd0303_recv;
s->i2c.send = ssd0303_send;
- s->console = graphic_console_init(ds, ssd0303_update_display,
- ssd0303_invalidate_display,
- NULL, NULL, s);
- qemu_console_resize(s->console, 96 * MAGNIFY, 16 * MAGNIFY);
+ s->ds = graphic_console_init(ssd0303_update_display,
+ ssd0303_invalidate_display,
+ NULL, NULL, s);
+ qemu_console_resize(s->ds, 96 * MAGNIFY, 16 * MAGNIFY);
register_savevm("ssd0303_oled", -1, 1, ssd0303_save, ssd0303_load, s);
}
typedef struct {
DisplayState *ds;
- QEMUConsole *console;
int cmd_len;
int cmd;
return 0;
}
-void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p)
+void *ssd0323_init(qemu_irq *cmd_p)
{
ssd0323_state *s;
qemu_irq *cmd;
s = (ssd0323_state *)qemu_mallocz(sizeof(ssd0323_state));
s->col_end = 63;
s->row_end = 79;
- s->ds = ds;
- s->console = graphic_console_init(ds, ssd0323_update_display,
- ssd0323_invalidate_display,
- NULL, NULL, s);
- qemu_console_resize(s->console, 128 * MAGNIFY, 64 * MAGNIFY);
+ s->ds = graphic_console_init(ssd0323_update_display,
+ ssd0323_invalidate_display,
+ NULL, NULL, s);
+ qemu_console_resize(s->ds, 128 * MAGNIFY, 64 * MAGNIFY);
cmd = qemu_allocate_irqs(ssd0323_cd, s, 1);
*cmd_p = *cmd;
};
static void stellaris_init(const char *kernel_filename, const char *cpu_model,
- DisplayState *ds, stellaris_board_info *board)
+ stellaris_board_info *board)
{
static const int uart_irq[] = {5, 6, 33, 34};
static const int timer_irq[] = {19, 21, 23, 35};
i2c = i2c_init_bus();
stellaris_i2c_init(0x40020000, pic[8], i2c);
if (board->peripherals & BP_OLED_I2C) {
- ssd0303_init(ds, i2c, 0x3d);
+ ssd0303_init(i2c, 0x3d);
}
}
void *ssi_bus;
int index;
- oled = ssd0323_init(ds, &gpio_out[GPIO_C][7]);
+ oled = ssd0323_init(&gpio_out[GPIO_C][7]);
index = drive_get_index(IF_SD, 0, 0);
sd = ssi_sd_init(drives_table[index].bdrv);
/* FIXME: Figure out how to generate these from stellaris_boards. */
static void lm3s811evb_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[0]);
+ stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
}
static void lm3s6965evb_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- stellaris_init(kernel_filename, cpu_model, ds, &stellaris_boards[1]);
+ stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
}
QEMUMachine lm3s811evb_machine = {
static void sun4m_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
- DisplayState *ds, const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
- tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
+ tcx_init(hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
if (nd_table[0].model == NULL
static void sun4c_hw_init(const struct hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
- DisplayState *ds, const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
- tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
+ tcx_init(hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
if (nd_table[0].model == NULL
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
+ sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&hwdefs[5], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&hwdefs[6], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&hwdefs[7], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&hwdefs[8], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, ds, kernel_filename,
+ sun4m_hw_init(&hwdefs[9], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
const char *boot_device,
- DisplayState *ds, const char *kernel_filename,
+ const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
exit (1);
}
- tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
+ tcx_init(hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
if (nd_table[0].model == NULL
/* SPARCserver 1000 hardware initialisation */
static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
+ sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
/* SPARCcenter 2000 hardware initialisation */
static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
+ sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model);
}
}
/* tcx.c */
-void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
+void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
unsigned long vram_offset, int vram_size, int width, int height,
int depth);
static fdctrl_t *floppy_controller;
static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_devices, DisplayState *ds,
+ const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
const struct hwdef *hwdef)
/* Sun4u hardware initialisation */
static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_devices, DisplayState *ds,
+ const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
+ sun4uv_init(RAM_size, vga_ram_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
}
/* Sun4v hardware initialisation */
static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_devices, DisplayState *ds,
+ const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
+ sun4uv_init(RAM_size, vga_ram_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
}
/* Niagara hardware initialisation */
static void niagara_init(ram_addr_t RAM_size, int vga_ram_size,
- const char *boot_devices, DisplayState *ds,
+ const char *boot_devices,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
- sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
+ sun4uv_init(RAM_size, vga_ram_size, boot_devices, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
}
typedef struct TCXState {
target_phys_addr_t addr;
DisplayState *ds;
- QEMUConsole *console;
uint8_t *vram;
uint32_t *vram24, *cplane;
ram_addr_t vram_offset, vram24_offset, cplane_offset;
tcx_dummy_writel,
};
-void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
+void tcx_init(target_phys_addr_t addr, uint8_t *vram_base,
unsigned long vram_offset, int vram_size, int width, int height,
int depth)
{
s = qemu_mallocz(sizeof(TCXState));
if (!s)
return;
- s->ds = ds;
s->addr = addr;
s->vram_offset = vram_offset;
s->width = width;
s->cplane = (uint32_t *)vram_base;
s->cplane_offset = vram_offset;
cpu_register_physical_memory(addr + 0x0a000000ULL, size, vram_offset);
- s->console = graphic_console_init(s->ds, tcx24_update_display,
- tcx24_invalidate_display,
- tcx24_screen_dump, NULL, s);
+ s->ds = graphic_console_init(tcx24_update_display,
+ tcx24_invalidate_display,
+ tcx24_screen_dump, NULL, s);
} else {
cpu_register_physical_memory(addr + 0x00300000ULL, TCX_THC_NREGS_8,
dummy_memory);
- s->console = graphic_console_init(s->ds, tcx_update_display,
- tcx_invalidate_display,
- tcx_screen_dump, NULL, s);
+ s->ds = graphic_console_init(tcx_update_display,
+ tcx_invalidate_display,
+ tcx_screen_dump, NULL, s);
}
// NetBSD writes here even with 8-bit display
cpu_register_physical_memory(addr + 0x00301000ULL, TCX_THC_NREGS_24,
register_savevm("tcx", addr, 4, tcx_save, tcx_load, s);
qemu_register_reset(tcx_reset, s);
tcx_reset(s);
- qemu_console_resize(s->console, width, height);
+ qemu_console_resize(s->ds, width, height);
}
static void tcx_screen_dump(void *opaque, const char *filename)
};
static void tosa_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
if (!cpu_model)
cpu_model = "pxa255";
- cpu = pxa255_init(tosa_binfo.ram_size, ds);
+ cpu = pxa255_init(tosa_binfo.ram_size);
cpu_register_physical_memory(0, TOSA_ROM,
qemu_ram_alloc(TOSA_ROM) | IO_MEM_ROM);
static struct arm_boot_info versatile_binfo;
static void versatile_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
int board_id)
/* The versatile/PB actually has a modified Color LCD controller
that includes hardware cursor support from the PL111. */
- pl110_init(ds, 0x10120000, pic[16], 1);
+ pl110_init(0x10120000, pic[16], 1);
index = drive_get_index(IF_SD, 0, 0);
if (index == -1) {
}
static void vpb_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
versatile_init(ram_size, vga_ram_size,
- boot_device, ds,
+ boot_device,
kernel_filename, kernel_cmdline,
initrd_filename, cpu_model, 0x183);
}
static void vab_init(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
versatile_init(ram_size, vga_ram_size,
- boot_device, ds,
+ boot_device,
kernel_filename, kernel_cmdline,
initrd_filename, cpu_model, 0x25e);
}
cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
s->last_scr_width = width * cw;
s->last_scr_height = height * cheight;
- qemu_console_resize(s->console, s->last_scr_width, s->last_scr_height);
- dpy_resize(s->ds);
+ qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
s->last_depth = 0;
s->last_width = width;
s->last_height = height;
cw != s->last_cw || cheight != s->last_ch) {
s->last_scr_width = width * cw;
s->last_scr_height = height * cheight;
- qemu_console_resize(s->console, s->last_scr_width, s->last_scr_height);
+ qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
s->last_width = width;
s->last_height = height;
s->last_ch = cheight;
#endif
dpy_resize(s->ds);
} else {
- qemu_console_resize(s->console, disp_width, height);
+ qemu_console_resize(s->ds, disp_width, height);
}
} else {
- qemu_console_resize(s->console, disp_width, height);
+ qemu_console_resize(s->ds, disp_width, height);
}
s->last_scr_width = disp_width;
s->last_scr_height = height;
}
/* when used on xen environment, the vga_ram_base is not used */
-void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
+void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
int i, j, v, b;
xen_vga_state = s;
s->vram_offset = vga_ram_offset;
s->vram_size = vga_ram_size;
- s->ds = ds;
s->get_bpp = vga_get_bpp;
s->get_offsets = vga_get_offsets;
s->get_resolution = vga_get_resolution;
s->vram_gmfn = VRAM_RESERVED_ADDRESS;
}
- graphic_console_init(s->ds, vga_update_display, vga_invalidate_display,
- vga_screen_dump, vga_update_text, s);
+ s->ds = graphic_console_init(vga_update_display, vga_invalidate_display,
+ vga_screen_dump, vga_update_text, s);
vga_bios_init(s);
switch (vga_retrace_method) {
vga_io_memory);
}
-int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
+int isa_vga_init(uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
VGAState *s;
vga_ram_size = 16*1024*1024;
}
- vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
+ vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_init(s);
#ifdef CONFIG_BOCHS_VBE
return 0;
}
-int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size,
unsigned long vga_bios_offset, int vga_bios_size)
{
vga_ram_size = 16*1024*1024;
}
- vga_common_init(s, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
+ vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
vga_init(s);
s->pci_dev = &d->dev;
VGA_STATE_COMMON_BOCHS_VBE \
/* display refresh support */ \
DisplayState *ds; \
- QEMUConsole *console; \
uint32_t font_offsets[2]; \
int graphic_mode; \
uint8_t shift_control; \
return (v << 2) | (b << 1) | b;
}
-void vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
+void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size);
uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
#ifndef EMBED_STDVGA
DisplayState *ds;
- QEMUConsole *console;
int vram_size;
ram_addr_t vram_offset;
#endif
# ifdef DIRECT_VRAM
if (s->ds->dpy_copy)
- qemu_console_copy(s->console, x0, y0, x1, y1, w, h);
+ qemu_console_copy(s->ds, x0, y0, x1, y1, w, h);
else
# endif
{
if (s->new_width != s->width || s->new_height != s->height) {
s->width = s->new_width;
s->height = s->new_height;
- qemu_console_resize(s->console, s->width, s->height);
+ qemu_console_resize(s->ds, s->width, s->height);
s->invalidated = 1;
}
}
s->width = -1;
s->height = -1;
s->svgaid = SVGA_ID;
- s->depth = ds_get_bits_per_pixel(s->ds) ? ds_get_bits_per_pixel(s->ds) : 24;
+ s->depth = 24;
s->bypp = (s->depth + 7) >> 3;
s->cursor.on = 0;
s->redraw_fifo_first = 0;
return 0;
}
-static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
+static void vmsvga_init(struct vmsvga_state_s *s,
uint8_t *vga_ram_base, unsigned long vga_ram_offset,
int vga_ram_size)
{
- s->ds = ds;
s->vram = vga_ram_base;
s->vram_size = vga_ram_size;
s->vram_offset = vga_ram_offset;
vmsvga_reset(s);
#ifdef EMBED_STDVGA
- vga_common_init((VGAState *) s, ds,
+ vga_common_init((VGAState *) s,
vga_ram_base, vga_ram_offset, vga_ram_size);
vga_init((VGAState *) s);
#endif
- s->console = graphic_console_init(ds, vmsvga_update_display,
- vmsvga_invalidate_display,
- vmsvga_screen_dump,
- vmsvga_text_update, s);
+ s->ds = graphic_console_init(vmsvga_update_display,
+ vmsvga_invalidate_display,
+ vmsvga_screen_dump,
+ vmsvga_text_update, s);
#ifdef CONFIG_BOCHS_VBE
/* XXX: use optimized standard vga accesses */
#define PCI_CLASS_SUB_VGA 0x00
#define PCI_CLASS_HEADERTYPE_00h 0x00
-void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size)
{
struct pci_vmsvga_state_s *s;
pci_register_io_region(&s->card, 1, vga_ram_size,
PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
- vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
+ vmsvga_init(&s->chip, vga_ram_base, vga_ram_offset, vga_ram_size);
register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
}
#else /*CONFIG_DM*/
-void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
+void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
unsigned long vga_ram_offset, int vga_ram_size) {
}
#endif
static void xen_init_fv(ram_addr_t ram_size, int vga_ram_size,
- const char *boot_device, DisplayState *ds,
+ const char *boot_device,
const char *kernel_filename,const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model,
const char *direct_pci)
timeoffset_get();
- pc_machine.init(ram_size, vga_ram_size, boot_device, ds,
+ pc_machine.init(ram_size, vga_ram_size, boot_device,
kernel_filename, kernel_cmdline, initrd_filename,
cpu_model, direct_pci);
}
if (xenfb->width != ds_get_width(xenfb->c.ds) || xenfb->height != ds_get_height(xenfb->c.ds)) {
xen_be_printf(&xenfb->c.xendev, 1, "update: resizing: %dx%d\n",
xenfb->width, xenfb->height);
- xenfb->c.ds->surface->width = xenfb->width;
- xenfb->c.ds->surface->height = xenfb->height;
- dpy_resize(xenfb->c.ds);
+ qemu_console_resize(xenfb->c.ds, xenfb->width, xenfb->height);
xenfb->up_fullscreen = 1;
}
return rc;
if (!fb->have_console) {
- graphic_console_init(fb->c.ds,
- xenfb_update,
- xenfb_invalidate,
- NULL,
- NULL,
- fb);
+ fb->c.ds = graphic_console_init(xenfb_update,
+ xenfb_invalidate,
+ NULL,
+ NULL,
+ fb);
fb->have_console = 1;
}
/* point to the block driver where the snapshots are managed */
static BlockDriverState *bs_snapshots;
enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB;
-static DisplayState display_state;
+static DisplayState *display_state;
int nographic;
static int curses;
static int sdl;
CharDriverState *chr;
if (!strcmp(filename, "vc")) {
- chr = text_console_init(&display_state, 0);
+ chr = text_console_init(0);
} else
if (strstart(filename, "vc:", &p)) {
- chr = text_console_init(&display_state, p);
+ chr = text_console_init(p);
} else
if (!strcmp(filename, "null")) {
chr = qemu_chr_open_null();
}
/***********************************************************/
-/* dumb display */
+/* register display */
-static void dumb_update(DisplayState *ds, int x, int y, int w, int h)
+void register_displaystate(DisplayState *ds)
{
+ DisplayState **s;
+ s = &display_state;
+ while (*s != NULL)
+ s = &(*s)->next;
+ ds->next = NULL;
+ *s = ds;
}
-static void dumb_resize(DisplayState *ds)
+DisplayState *get_displaystate(void)
{
+ return display_state;
}
-static void dumb_refresh(DisplayState *ds)
-{
-#if defined(CONFIG_SDL)
- vga_hw_update();
-#endif
-}
+/* dumb display */
-static void dumb_display_init(DisplayState *ds)
+static void dumb_display_init(void)
{
- DisplayChangeListener *dcl = qemu_mallocz(sizeof(DisplayChangeListener));
- if (!dcl)
+ DisplayState *ds = qemu_mallocz(sizeof(DisplayState));
+ if (ds == NULL) {
+ fprintf(stderr, "dumb_display_init: DisplayState allocation failed\n");
exit(1);
- dcl->dpy_update = dumb_update;
- dcl->dpy_resize = dumb_resize;
- dcl->dpy_refresh = NULL;
- dcl->idle = 1;
- dcl->gui_timer_interval = 500;
- register_displaychangelistener(ds, dcl);
+ }
+ ds->surface = qemu_create_displaysurface(640, 480, 32, 640 * 4);
+ register_displaystate(ds);
}
/***********************************************************/
const char *initrd_filename;
const char *kernel_filename, *kernel_cmdline;
const char *boot_devices = "";
- DisplayState *ds = &display_state;
+ DisplayState *ds;
DisplayChangeListener *dcl;
int cyls, heads, secs, translation;
const char *net_clients[MAX_NET_CLIENTS];
int hda_index;
int optind;
const char *r, *optarg;
- CharDriverState *monitor_hd;
+ CharDriverState *monitor_hd = NULL;
const char *monitor_device;
const char *serial_devices[MAX_SERIAL_PORTS];
int serial_device_index;
register_savevm("timer", 0, 2, timer_save, timer_load, NULL);
register_savevm_live("ram", 0, 3, ram_save_live, NULL, ram_load, NULL);
+#ifndef _WIN32
+ /* must be after terminal init, SDL library changes signal handlers */
+ termsig_setup();
+#endif
+
+ /* Maintain compatibility with multiple stdio monitors */
+ if (!strcmp(monitor_device,"stdio")) {
+ for (i = 0; i < MAX_SERIAL_PORTS; i++) {
+ const char *devname = serial_devices[i];
+ if (devname && !strcmp(devname,"mon:stdio")) {
+ monitor_device = NULL;
+ break;
+ } else if (devname && !strcmp(devname,"stdio")) {
+ monitor_device = NULL;
+ serial_devices[i] = "mon:stdio";
+ break;
+ }
+ }
+ }
+
+ if (monitor_device) {
+ monitor_hd = qemu_chr_open("monitor", monitor_device);
+ if (!monitor_hd) {
+ fprintf(stderr, "qemu: could not open monitor device '%s'\n", monitor_device);
+ exit(1);
+ }
+ }
+
+ for(i = 0; i < MAX_SERIAL_PORTS; i++) {
+ const char *devname = serial_devices[i];
+ if (devname && strcmp(devname, "none")) {
+ char label[32];
+ snprintf(label, sizeof(label), "serial%d", i);
+ serial_hds[i] = qemu_chr_open(label, devname);
+ if (!serial_hds[i]) {
+ fprintf(stderr, "qemu: could not open serial device '%s'\n",
+ devname);
+ exit(1);
+ }
+ }
+ }
+
+ for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
+ const char *devname = parallel_devices[i];
+ if (devname && strcmp(devname, "none")) {
+ char label[32];
+ snprintf(label, sizeof(label), "parallel%d", i);
+ parallel_hds[i] = qemu_chr_open(label, devname);
+ if (!parallel_hds[i]) {
+ fprintf(stderr, "qemu: could not open parallel device '%s'\n",
+ devname);
+ exit(1);
+ }
+ }
+ }
+
+ machine->init(ram_size, vga_ram_size, boot_devices,
+ kernel_filename, kernel_cmdline, initrd_filename, cpu_model,
+ direct_pci);
+
+ /* init USB devices */
+ if (usb_enabled) {
+ for(i = 0; i < usb_devices_index; i++) {
+ if (usb_device_add(usb_devices[i]) < 0) {
+ fprintf(stderr, "Warning: could not add USB device %s\n",
+ usb_devices[i]);
+ }
+ }
+ }
+
+ if (!display_state)
+ dumb_display_init();
+ /* just use the first displaystate for the moment */
+ ds = display_state;
/* terminal init */
- memset(&display_state, 0, sizeof(display_state));
- ds->surface = qemu_create_displaysurface(640, 480, 32, 640 * 4);
#ifdef CONFIG_STUBDOM
if (xenfb_pv_display_init(ds) == 0) {
} else
}
dpy_resize(ds);
-#ifndef _WIN32
- /* must be after terminal init, SDL library changes signal handlers */
- termsig_setup();
-#endif
-
- /* Maintain compatibility with multiple stdio monitors */
- if (!strcmp(monitor_device,"stdio")) {
- for (i = 0; i < MAX_SERIAL_PORTS; i++) {
- const char *devname = serial_devices[i];
- if (devname && !strcmp(devname,"mon:stdio")) {
- monitor_device = NULL;
- break;
- } else if (devname && !strcmp(devname,"stdio")) {
- monitor_device = NULL;
- serial_devices[i] = "mon:stdio";
- break;
- }
+ dcl = ds->listeners;
+ while (dcl != NULL) {
+ if (dcl->dpy_refresh != NULL) {
+ ds->gui_timer = qemu_new_timer(rt_clock, gui_update, ds);
+ qemu_mod_timer(ds->gui_timer, qemu_get_clock(rt_clock));
}
+ dcl = dcl->next;
}
- if (monitor_device) {
- monitor_hd = qemu_chr_open("monitor", monitor_device);
- if (!monitor_hd) {
- fprintf(stderr, "qemu: could not open monitor device '%s'\n", monitor_device);
- exit(1);
- }
+
+ text_consoles_set_display(display_state);
+
+ if (monitor_device && monitor_hd) {
monitor_init(monitor_hd, !nographic);
}
if (devname && strcmp(devname, "none")) {
char label[32];
snprintf(label, sizeof(label), "serial%d", i);
- serial_hds[i] = qemu_chr_open(label, devname);
- if (!serial_hds[i]) {
- fprintf(stderr, "qemu: could not open serial device '%s'\n",
- devname);
- exit(1);
- }
if (strstart(devname, "vc", 0))
qemu_chr_printf(serial_hds[i], "serial%d console\r\n", i);
xenstore_store_serial_port_info(i, serial_hds[i], devname);
if (devname && strcmp(devname, "none")) {
char label[32];
snprintf(label, sizeof(label), "parallel%d", i);
- parallel_hds[i] = qemu_chr_open(label, devname);
- if (!parallel_hds[i]) {
- fprintf(stderr, "qemu: could not open parallel device '%s'\n",
- devname);
- exit(1);
- }
if (strstart(devname, "vc", 0))
qemu_chr_printf(parallel_hds[i], "parallel%d console\r\n", i);
}
if (strlen(direct_pci_str) > 0)
direct_pci = direct_pci_str;
- machine->init(ram_size, vga_ram_size, boot_devices, ds,
- kernel_filename, kernel_cmdline, initrd_filename, cpu_model,
- direct_pci);
-
- /* init USB devices */
- if (usb_enabled) {
- for(i = 0; i < usb_devices_index; i++) {
- if (usb_device_add(usb_devices[i]) < 0) {
- fprintf(stderr, "Warning: could not add USB device %s\n",
- usb_devices[i]);
- }
- }
- }
-
- dcl = ds->listeners;
- while (dcl != NULL) {
- if (dcl->dpy_refresh != NULL) {
- display_state.gui_timer = qemu_new_timer(rt_clock, gui_update, &display_state);
- qemu_mod_timer(display_state.gui_timer, qemu_get_clock(rt_clock));
- }
- dcl = dcl->next;
- }
-
#ifdef CONFIG_GDBSTUB
if (use_gdbstub) {
/* XXX: use standard host:port notation and modify options
projects / qemu-xen-3.4-testing.git / commitdiff