S390CPU *ipl_cpu = S390_CPU(qemu_get_cpu(0));
qemu_devices_reset();
+ s390_cmma_reset();
s390_crypto_reset();
/* all cpus are stopped - configure and start the ipl cpu only */
int vq, bool assign);
int kvm_s390_cpu_restart(S390CPU *cpu);
int kvm_s390_get_memslot_count(KVMState *s);
-void kvm_s390_clear_cmma_callback(void *opaque);
+void kvm_s390_cmma_reset(void);
int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
void kvm_s390_reset_vcpu(S390CPU *cpu);
int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
{
return -ENOSYS;
}
-static inline void kvm_s390_clear_cmma_callback(void *opaque)
+static inline void kvm_s390_cmma_reset(void)
{
}
static inline int kvm_s390_get_memslot_count(KVMState *s)
return 0;
}
-static inline void cmma_reset(S390CPU *cpu)
+static inline void s390_cmma_reset(void)
{
if (kvm_enabled()) {
- CPUState *cs = CPU(cpu);
- kvm_s390_clear_cmma_callback(cs->kvm_state);
+ kvm_s390_cmma_reset();
}
}
return kvm_vm_ioctl(s, KVM_SET_DEVICE_ATTR, &attr);
}
-void kvm_s390_clear_cmma_callback(void *opaque)
+void kvm_s390_cmma_reset(void)
{
int rc;
- KVMState *s = opaque;
struct kvm_device_attr attr = {
.group = KVM_S390_VM_MEM_CTRL,
.attr = KVM_S390_VM_MEM_CLR_CMMA,
};
- rc = kvm_vm_ioctl(s, KVM_SET_DEVICE_ATTR, &attr);
+ rc = kvm_vm_ioctl(kvm_state, KVM_SET_DEVICE_ATTR, &attr);
trace_kvm_clear_cmma(rc);
}
}
rc = kvm_vm_ioctl(s, KVM_SET_DEVICE_ATTR, &attr);
- if (!rc) {
- qemu_register_reset(kvm_s390_clear_cmma_callback, s);
- }
trace_kvm_enable_cmma(rc);
}
CPU_FOREACH(t) {
run_on_cpu(t, s390_do_cpu_full_reset, t);
}
- cmma_reset(cpu);
+ s390_cmma_reset();
subsystem_reset();
s390_crypto_reset();
scc->load_normal(CPU(cpu));
CPU_FOREACH(t) {
run_on_cpu(t, s390_do_cpu_reset, t);
}
- cmma_reset(cpu);
+ s390_cmma_reset();
subsystem_reset();
scc->initial_cpu_reset(CPU(cpu));
scc->load_normal(CPU(cpu));