]> xenbits.xensource.com Git - xen.git/commitdiff
amd iommu: add 2 helper functions: iommu_is_pte_present and iommu_next_level
authorWei Wang <wei.wang2@amd.com>
Tue, 11 Sep 2012 12:00:04 +0000 (14:00 +0200)
committerWei Wang <wei.wang2@amd.com>
Tue, 11 Sep 2012 12:00:04 +0000 (14:00 +0200)
Signed-off-by: Wei Wang <wei.wang2@amd.com>
Committed-by: Jan Beulich <jbeulich@suse.com>
xen/drivers/passthrough/amd/iommu_map.c
xen/drivers/passthrough/amd/pci_amd_iommu.c
xen/include/asm-x86/hvm/svm/amd-iommu-proto.h

index 43bf5e53a254ee1e30456c059fce594df57b8760..542f88bc5b3cff4273a804dc7a205800c88db9e8 100644 (file)
@@ -306,20 +306,6 @@ u64 amd_iommu_get_next_table_from_pte(u32 *entry)
     return ptr;
 }
 
-static unsigned int iommu_next_level(u32 *entry)
-{
-    return get_field_from_reg_u32(entry[0],
-                                  IOMMU_PDE_NEXT_LEVEL_MASK,
-                                  IOMMU_PDE_NEXT_LEVEL_SHIFT);
-}
-
-static int amd_iommu_is_pte_present(u32 *entry)
-{
-    return get_field_from_reg_u32(entry[0],
-                                  IOMMU_PDE_PRESENT_MASK,
-                                  IOMMU_PDE_PRESENT_SHIFT);
-}
-
 /* For each pde, We use ignored bits (bit 1 - bit 8 and bit 63)
  * to save pde count, pde count = 511 is a candidate of page coalescing.
  */
@@ -489,7 +475,7 @@ static int iommu_pde_from_gfn(struct domain *d, unsigned long pfn,
                          >> PAGE_SHIFT;
 
         /* Split super page frame into smaller pieces.*/
-        if ( amd_iommu_is_pte_present((u32*)pde) &&
+        if ( iommu_is_pte_present((u32*)pde) &&
              (iommu_next_level((u32*)pde) == 0) &&
              next_table_mfn != 0 )
         {
@@ -526,7 +512,7 @@ static int iommu_pde_from_gfn(struct domain *d, unsigned long pfn,
         }
 
         /* Install lower level page table for non-present entries */
-        else if ( !amd_iommu_is_pte_present((u32*)pde) )
+        else if ( !iommu_is_pte_present((u32*)pde) )
         {
             if ( next_table_mfn == 0 )
             {
index f2db0d64efe9769e5a0befc8e030aea9ed3a1824..ad2401803361acb95c25049570fd74d68761c889 100644 (file)
@@ -393,8 +393,7 @@ static void deallocate_next_page_table(struct page_info* pg, int level)
 {
     void *table_vaddr, *pde;
     u64 next_table_maddr;
-    int index, next_level, present;
-    u32 *entry;
+    int index, next_level;
 
     table_vaddr = __map_domain_page(pg);
 
@@ -404,18 +403,11 @@ static void deallocate_next_page_table(struct page_info* pg, int level)
         {
             pde = table_vaddr + (index * IOMMU_PAGE_TABLE_ENTRY_SIZE);
             next_table_maddr = amd_iommu_get_next_table_from_pte(pde);
-            entry = (u32*)pde;
-
-            next_level = get_field_from_reg_u32(entry[0],
-                                                IOMMU_PDE_NEXT_LEVEL_MASK,
-                                                IOMMU_PDE_NEXT_LEVEL_SHIFT);
 
-            present = get_field_from_reg_u32(entry[0],
-                                             IOMMU_PDE_PRESENT_MASK,
-                                             IOMMU_PDE_PRESENT_SHIFT);
+            next_level = iommu_next_level((u32*)pde);
 
             if ( (next_table_maddr != 0) && (next_level != 0)
-                && present )
+                && iommu_is_pte_present((u32*)pde) )
             {
                 deallocate_next_page_table(
                     maddr_to_page(next_table_maddr), level - 1);
index a41acde3271be1f123e0962faacbc6124d17502a..8c425a3d1b747e5238cbceb4b87362d8c7b09e8e 100644 (file)
@@ -257,4 +257,18 @@ static inline void iommu_set_addr_hi_to_reg(uint32_t *reg, uint32_t addr)
                          IOMMU_REG_BASE_ADDR_HIGH_SHIFT, reg);
 }
 
+static inline int iommu_is_pte_present(const u32 *entry)
+{
+    return get_field_from_reg_u32(entry[0],
+                                  IOMMU_PDE_PRESENT_MASK,
+                                  IOMMU_PDE_PRESENT_SHIFT);
+}
+
+static inline unsigned int iommu_next_level(const u32 *entry)
+{
+    return get_field_from_reg_u32(entry[0],
+                                  IOMMU_PDE_NEXT_LEVEL_MASK,
+                                  IOMMU_PDE_NEXT_LEVEL_SHIFT);
+}
+
 #endif /* _ASM_X86_64_AMD_IOMMU_PROTO_H */