uint32_t mask;
uint8_t offset;
+ if ((size & (size - 1)) != 0) {
+ int n = __builtin_clzl(size);
+
+ size = 1ul << (64 - n);
+ }
+
DBG("%d: %"PRIx64"\n", index, size);
if (index >= PCI_NUM_BAR)
vga_state.vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
vga_state.vbe_bank_mask = ((vga_state.vram_size >> 16) - 1);
- rc = demu_register_port_space(0x1ce, 2, &vbe_port_ops, NULL);
+ rc = demu_register_port_space(0x1ce, 4, &vbe_port_ops, NULL);
if (rc < 0)
goto fail6;
- rc = demu_register_port_space(0xff80, 2, &vbe_port_ops, NULL);
+ rc = demu_register_port_space(0xff80, 4, &vbe_port_ops, NULL);
if (rc < 0)
goto fail7;