x86: Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS

Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS

There is a new hardware feature, which lets system software to set
Energy Performance Preference. This is a opaque knob in the form of
IA32_ENERGY_PERF_BIAS MSR, which has a 4 bit Energy Performance
Preference Hint.

The support for this feature is indicated by CPUID.06H.ECX.bit3. Refer
to Intel Architectures Software Developer's Manual for more info.

Let dom0 tools to control it.

Signed-off-by: Wei Gang <gang.wei@intel.com>

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index 0c4b5441d765ce7abd64c60c47172e65ab99cc7d..ad4231cec4bb5854be3376716a0b801122905a2e 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -2333,6 +2333,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs)
                 goto fail;
             break;
         case MSR_IA32_THERM_CONTROL:
+        case MSR_IA32_ENERGY_PERF_BIAS:
             if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL )
                 goto fail;
             if ( (v->domain->domain_id != 0) || !v->domain->is_pinned )

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index cc32932cd498c4f32a76e93882f1c89c2447224d..316a1931cdbe52873bc1609998ae4c61dee6b718 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -330,6 +330,7 @@
 #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23)
 
 #define MSR_IA32_TSC_DEADLINE          0x000006E0
+#define MSR_IA32_ENERGY_PERF_BIAS      0x000001b0
 
 /* Intel Model 6 */
 #define MSR_P6_EVNTSEL0                        0x00000186