x86: update Intel CPUID masking code to latest spec

..., which adds masking of the xsave feature leaf.

Also add back (and fix to actually make it do what it was supposed to
do from the beginning) the printing of what specific masking couldn't
be done in case the user requested something the hardware doesn't
support.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
xen-unstable changeset:   23726:fd97ca086df6
xen-unstable date:        Tue Jul 19 14:14:51 2011 +0100

x86: add change missing in c/s 23726:fd97ca086df6

The early "do we need to do anything" check needs adjustment, too.
Thanks to Haitao Shan for pointing this out.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
xen-unstable changeset:   23731:48f72b389b04
xen-unstable date:        Thu Jul 21 14:34:51 2011 +0100

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index aa408dc673e94d83a0c157466cc553d891142c29..ceec7b755a747ea42af8811f89f3cb7f21eaccd8 100644 (file)
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -27,10 +27,15 @@ boolean_param("noserialnumber", disable_x86_serial_nr);
 
 static bool_t __cpuinitdata use_xsave;
 boolean_param("xsave", use_xsave);
+
 unsigned int __devinitdata opt_cpuid_mask_ecx = ~0u;
 integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
 unsigned int __devinitdata opt_cpuid_mask_edx = ~0u;
 integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
+
+unsigned int __devinitdata opt_cpuid_mask_xsave_eax = ~0u;
+integer_param("cpuid_mask_xsave_eax", opt_cpuid_mask_xsave_eax);
+
 unsigned int __devinitdata opt_cpuid_mask_ext_ecx = ~0u;
 integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);
 unsigned int __devinitdata opt_cpuid_mask_ext_edx = ~0u;

diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index a696859ff6ca0f50a040e3910117b7654df552ee..16e99ea36650472b0da893d5b219dce54a52648d 100644 (file)
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -22,6 +22,7 @@ struct cpu_dev {
 extern struct cpu_dev * cpu_devs [X86_VENDOR_NUM];
 
 extern unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
+extern unsigned int opt_cpuid_mask_xsave_eax;
 extern unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
 
 extern int get_model_name(struct cpuinfo_x86 *c);

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 0bfb883c4bbbf662597b3e61715764c68c8a7d0e..81e6fde9c194764e62fad11bb511ae8f9e35ba5a 100644 (file)
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -59,10 +59,12 @@ void set_cpuid_faulting(bool_t enable)
  */
 static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
 {
+       u32 eax, edx;
        const char *extra = "";
 
        if (!~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx &
-              opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
+              opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx &
+               opt_cpuid_mask_xsave_eax))
                return;
 
        /* Only family 6 supports this feature  */
@@ -75,7 +77,11 @@ static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
                wrmsr(MSR_INTEL_CPUID_FEATURE_MASK,
                      opt_cpuid_mask_ecx,
                      opt_cpuid_mask_edx);
-               if (!~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
+               if (~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
+                       extra = "extended ";
+               else if (~opt_cpuid_mask_xsave_eax)
+                       extra = "xsave ";
+               else
                        return;
                extra = "extended ";
                break;
@@ -97,11 +103,25 @@ static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
                wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK,
                      opt_cpuid_mask_ext_ecx,
                      opt_cpuid_mask_ext_edx);
+               if (!~opt_cpuid_mask_xsave_eax)
+                       return;
+               extra = "xsave ";
+               break;
+       case 0x2a:
+               wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK_V2,
+                     opt_cpuid_mask_ecx,
+                     opt_cpuid_mask_edx);
+               rdmsr(MSR_INTEL_CPUIDD_01_FEATURE_MASK, eax, edx);
+               wrmsr(MSR_INTEL_CPUIDD_01_FEATURE_MASK,
+                     opt_cpuid_mask_xsave_eax, edx);
+               wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK_V2,
+                     opt_cpuid_mask_ext_ecx,
+                     opt_cpuid_mask_ext_edx);
                return;
        }
 
-       printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
-              smp_processor_id());
+       printk(XENLOG_ERR "Cannot set CPU %sfeature mask on CPU#%d\n",
+              extra, smp_processor_id());
 }
 
 void __devinit early_intel_workaround(struct cpuinfo_x86 *c)

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 556217bd4f797971963973e596895fd21a3496ec..f97afd6be230beedff9fb7e9355e94c085ba8eea 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -495,6 +495,10 @@
 #define MSR_INTEL_CPUID1_FEATURE_MASK  0x00000130
 #define MSR_INTEL_CPUID80000001_FEATURE_MASK 0x00000131
 
+#define MSR_INTEL_CPUID1_FEATURE_MASK_V2        0x00000132
+#define MSR_INTEL_CPUID80000001_FEATURE_MASK_V2 0x00000133
+#define MSR_INTEL_CPUIDD_01_FEATURE_MASK        0x00000134
+
 /* Intel cpuid faulting MSRs */
 #define MSR_INTEL_PLATFORM_INFO                0x000000ce
 #define MSR_INTEL_MISC_FEATURES_ENABLES        0x00000140