svm: allow guest to use EFER.FFXSE

Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Keir Fraser <keir@xensource.com>

diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 0b8477eb6574e41d8dcdbba0296ad0217a2d82c8..60499931a2d14242f02f6ab2d2c4fa704963cf6b 100644 (file)
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -358,10 +358,12 @@ static int hvm_load_cpu_ctxt(struct domain *d, hvm_domain_context_t *h)
         return -EINVAL;
     }
 
-    if ( (ctxt.msr_efer & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE)) ||
+    if ( (ctxt.msr_efer & ~(EFER_FFXSE | EFER_LME | EFER_LMA |
+                            EFER_NX | EFER_SCE)) ||
          ((sizeof(long) != 8) && (ctxt.msr_efer & EFER_LME)) ||
          (!cpu_has_nx && (ctxt.msr_efer & EFER_NX)) ||
          (!cpu_has_syscall && (ctxt.msr_efer & EFER_SCE)) ||
+         (!cpu_has_ffxsr && (ctxt.msr_efer & EFER_FFXSE)) ||
          ((ctxt.msr_efer & (EFER_LME|EFER_LMA)) == EFER_LMA) )
     {
         gdprintk(XENLOG_ERR, "HVM restore: bad EFER 0x%"PRIx64"\n",
@@ -576,10 +578,11 @@ int hvm_set_efer(uint64_t value)
 
     value &= ~EFER_LMA;
 
-    if ( (value & ~(EFER_LME | EFER_NX | EFER_SCE)) ||
+    if ( (value & ~(EFER_FFXSE | EFER_LME | EFER_NX | EFER_SCE)) ||
          ((sizeof(long) != 8) && (value & EFER_LME)) ||
          (!cpu_has_nx && (value & EFER_NX)) ||
-         (!cpu_has_syscall && (value & EFER_SCE)) )
+         (!cpu_has_syscall && (value & EFER_SCE)) ||
+         (!cpu_has_ffxsr && (value & EFER_FFXSE)) )
     {
         gdprintk(XENLOG_WARNING, "Trying to set reserved bit in "
                  "EFER: %"PRIx64"\n", value);

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index e85f70a12511967d09fa1de4b1e9b2c96bb2a365..2e5655e02c1639c294bf5536bad50cc8d1265e59 100644 (file)
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -1036,8 +1036,6 @@ static void svm_vmexit_do_cpuid(struct vmcb_struct *vmcb,
         /* So far, we do not support 3DNow for the guest. */
         clear_bit(X86_FEATURE_3DNOW & 31, &edx);
         clear_bit(X86_FEATURE_3DNOWEXT & 31, &edx);
-        /* no FFXSR instructions feature. */
-        clear_bit(X86_FEATURE_FFXSR & 31, &edx);
     }
     else if ( input == 0x80000007 || input == 0x8000000A )
     {

diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 9504ea040d19553afbb5b8d0efcb28a97fcd78ba..194e7affebf4f3ca8201d18b3145488402b62aa8 100644 (file)
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -49,6 +49,7 @@
 #define X86_FEATURE_MP         (1*32+19) /* MP Capable. */
 #define X86_FEATURE_NX         (1*32+20) /* Execute Disable */
 #define X86_FEATURE_MMXEXT     (1*32+22) /* AMD MMX extensions */
+#define X86_FEATURE_FFXSR       (1*32+25) /* FFXSR instruction optimizations */
 #define X86_FEATURE_RDTSCP     (1*32+27) /* RDTSCP */
 #define X86_FEATURE_LM         (1*32+29) /* Long Mode (x86-64) */
 #define X86_FEATURE_3DNOWEXT   (1*32+30) /* AMD 3DNow! extensions */
@@ -94,7 +95,6 @@
 #define X86_FEATURE_LAHF_LM    (6*32+ 0) /* LAHF/SAHF in long mode */
 #define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
 #define X86_FEATURE_SVME        (6*32+ 2) /* Secure Virtual Machine */
-#define X86_FEATURE_FFXSR       (6*32+25) /* FFXSR instruction optimizations */
 
 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)
@@ -147,6 +147,9 @@
 #define cpu_has_clflush                boot_cpu_has(X86_FEATURE_CLFLSH)
 #endif
 
+#define cpu_has_ffxsr           ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) \
+                                 && boot_cpu_has(X86_FEATURE_FFXSR))
+
 #endif /* __ASM_I386_CPUFEATURE_H */
 
 /* 

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index c2bbb2a5a32ed022ad4c67c9627ae00fef55a8dd..28f0a3c84f95fa4c408052d667433673040ddd51 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -18,13 +18,17 @@
 #define _EFER_LME              8  /* Long mode enable */
 #define _EFER_LMA              10 /* Long mode active (read-only) */
 #define _EFER_NX               11 /* No execute enable */
-#define _EFER_SVME             12
+#define _EFER_SVME             12 /* AMD: SVM enable */
+#define _EFER_LMSLE            13 /* AMD: Long-mode segment limit enable */
+#define _EFER_FFXSE            14 /* AMD: Fast FXSAVE/FXRSTOR enable */
 
 #define EFER_SCE               (1<<_EFER_SCE)
 #define EFER_LME               (1<<_EFER_LME)
 #define EFER_LMA               (1<<_EFER_LMA)
 #define EFER_NX                        (1<<_EFER_NX)
 #define EFER_SVME              (1<<_EFER_SVME)
+#define EFER_LMSLE             (1<<_EFER_LMSLE)
+#define EFER_FFXSE             (1<<_EFER_FFXSE)
 
 /* Intel MSRs. Some also available on other CPUs */
 #define MSR_IA32_PERFCTR0              0x000000c1