u32 pm_tmr = le32_to_cpu(fadt->pm_tmr_blk);
dprintf(4, "pm_tmr_blk=%x\n", pm_tmr);
if (pm_tmr)
- pmtimer_setup(pm_tmr, 3579);
+ pmtimer_setup(pm_tmr);
// Theoretically we should check the 'reset_reg_sup' flag, but Windows
// doesn't and thus nobody seems to *set* it. If the table is large enough
#include "dev-q35.h" // Q35_HOST_BRIDGE_PCIEXBAR_ADDR
#include "list.h" // struct hlist_node
-/* PM Timer ticks per second (HZ) */
-#define PM_TIMER_FREQUENCY 3579545
-
#define PCI_DEVICE_MEM_MIN 0x1000
#define PCI_BRIDGE_IO_MIN 0x1000
#define PCI_BRIDGE_MEM_MIN 0x100000
/* acpi enable, SCI: IRQ9 000b = irq9*/
pci_config_writeb(bdf, ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_ACPI_EN);
- pmtimer_setup(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000);
+ pmtimer_setup(PORT_ACPI_PM_BASE + 0x08);
}
static void storage_ide_setup(struct pci_device *pci, void *arg)
pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
- pmtimer_setup(PORT_ACPI_PM_BASE + 0x08, PM_TIMER_FREQUENCY / 1000);
+ pmtimer_setup(PORT_ACPI_PM_BASE + 0x08);
}
/* ICH9 SMBUS */
#ifndef __PIT_H
#define __PIT_H
+/* PM Timer ticks per second (HZ) */
+#define PM_TIMER_FREQUENCY 3579545
+
#define PIT_TICK_RATE 1193180 // Underlying HZ of PIT
#define PIT_TICK_INTERVAL 65536 // Default interval for 18.2Hz timer
#define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
return ret;
}
-void pmtimer_setup(u16 ioport, u32 khz)
+void pmtimer_setup(u16 ioport)
{
if (!CONFIG_PMTIMER)
return;
+ u32 khz = PM_TIMER_FREQUENCY / 1000;
dprintf(1, "Using pmtimer, ioport 0x%x, freq %d kHz\n", ioport, khz);
SET_GLOBAL(pmtimer_ioport, ioport);
SET_GLOBAL(cpu_khz, khz);
void releaseRTC(void);
// timer.c
-void pmtimer_setup(u16 ioport, u32 khz);
+void pmtimer_setup(u16 ioport);
int check_tsc(u64 end);
void timer_setup(void);
void ndelay(u32 count);