/*
* # of IRQ routing registers
*/
-int __read_mostly nr_ioapic_registers[MAX_IO_APICS];
+int __read_mostly nr_ioapic_entries[MAX_IO_APICS];
int __read_mostly nr_ioapics;
/*
for (apic = 0; apic < nr_ioapics; apic++) {
ioapic_entries[apic] =
xmalloc_array(struct IO_APIC_route_entry,
- nr_ioapic_registers[apic]);
+ nr_ioapic_entries[apic]);
if (!ioapic_entries[apic])
goto nomem;
}
if ( pin == -1 )
{
unsigned int p;
- for ( p = 0; p < nr_ioapic_registers[apic]; ++p )
+ for ( p = 0; p < nr_ioapic_entries[apic]; ++p )
{
entry = __ioapic_read_entry(apic, p, TRUE);
if ( entry.vector == vector )
if (!ioapic_entries[apic])
return -ENOMEM;
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
+ for (pin = 0; pin < nr_ioapic_entries[apic]; pin++)
ioapic_entries[apic][pin] = __ioapic_read_entry(apic, pin, 1);
}
if (!ioapic_entries[apic])
break;
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
+ for (pin = 0; pin < nr_ioapic_entries[apic]; pin++) {
struct IO_APIC_route_entry entry;
entry = ioapic_entries[apic][pin];
if (!ioapic_entries[apic])
return -ENOMEM;
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
+ for (pin = 0; pin < nr_ioapic_entries[apic]; pin++)
ioapic_write_entry(apic, pin, 1, ioapic_entries[apic][pin]);
}
int apic, pin;
for (apic = 0; apic < nr_ioapics; apic++) {
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
+ for (pin = 0; pin < nr_ioapic_entries[apic]; pin++)
clear_IO_APIC_pin(apic, pin);
}
}
return;
for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
- for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
+ for (pin = 0; pin < nr_ioapic_entries[ioapic]; pin++) {
irq_entry = find_irq_entry(ioapic, pin, mp_INT);
if (irq_entry == -1)
continue;
*/
i = irq = 0;
while (i < apic)
- irq += nr_ioapic_registers[i++];
+ irq += nr_ioapic_entries[i++];
irq += pin;
break;
}
int apic, idx, pin;
for (apic = 0; apic < nr_ioapics; apic++) {
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
+ for (pin = 0; pin < nr_ioapic_entries[apic]; pin++) {
idx = find_irq_entry(apic,pin,mp_INT);
if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
return irq_trigger(idx);
apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
for (apic = 0; apic < nr_ioapics; apic++) {
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
+ for (pin = 0; pin < nr_ioapic_entries[apic]; pin++) {
/*
* add it to the IO-APIC irq-routing table:
printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
for (i = 0; i < nr_ioapics; i++)
printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
- mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
+ mp_ioapics[i].mpc_apicid, nr_ioapic_entries[i]);
/*
* We are a bit conservative about what we expect. We have to
for(apic = 0; apic < nr_ioapics; apic++) {
int pin;
/* See if any of the pins is in ExtINT mode */
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
+ for (pin = 0; pin < nr_ioapic_entries[apic]; pin++) {
struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin, 0);
/* If the interrupt line is enabled and in ExtInt mode
int i, nr_entry = 0;
for (i = 0; i < nr_ioapics; i++)
- nr_entry += nr_ioapic_registers[i];
+ nr_entry += nr_ioapic_entries[i];
ioapic_pm_state = _xmalloc(sizeof(struct IO_APIC_route_entry)*nr_entry,
sizeof(struct IO_APIC_route_entry));
spin_lock_irqsave(&ioapic_lock, flags);
for (apic = 0; apic < nr_ioapics; apic++) {
- for (i = 0; i < nr_ioapic_registers[apic]; i ++, entry ++ ) {
+ for (i = 0; i < nr_ioapic_entries[apic]; i ++, entry ++ ) {
*(((int *)entry) + 1) = __io_apic_read(apic, 0x11 + 2 * i);
*(((int *)entry) + 0) = __io_apic_read(apic, 0x10 + 2 * i);
}
reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
__io_apic_write(apic, 0, reg_00.raw);
}
- for (i = 0; i < nr_ioapic_registers[apic]; i++, entry++) {
+ for (i = 0; i < nr_ioapic_entries[apic]; i++, entry++) {
__io_apic_write(apic, 0x11+2*i, *(((int *)entry)+1));
__io_apic_write(apic, 0x10+2*i, *(((int *)entry)+0));
}
{
/* The number of IO-APIC IRQ registers (== #pins): */
reg_01.raw = io_apic_read(i, 1);
- nr_ioapic_registers[i] = reg_01.bits.entries + 1;
- nr_irqs_gsi += nr_ioapic_registers[i];
+ nr_ioapic_entries[i] = reg_01.bits.entries + 1;
+ nr_irqs_gsi += nr_ioapic_entries[i];
}
}
#ifdef __ia64__
#define nr_ioapics iosapic_get_nr_iosapics()
-#define nr_ioapic_registers(i) iosapic_get_nr_pins(i)
+#define nr_ioapic_entries(i) iosapic_get_nr_pins(i)
#define __io_apic_read(apic, reg) \
(*IO_APIC_BASE(apic) = reg, *(IO_APIC_BASE(apic)+4))
#define __io_apic_write(apic, reg, val) \
#else
#include <asm/apic.h>
#include <asm/io_apic.h>
-#define nr_ioapic_registers(i) nr_ioapic_registers[i]
+#define nr_ioapic_entries(i) nr_ioapic_entries[i]
#endif
/*
nr_pins = 0;
for ( i = 0; i < nr_ioapics; i++ )
- nr_pins += nr_ioapic_registers(i);
+ nr_pins += nr_ioapic_entries(i);
_apic_pin_2_ir_idx = xmalloc_array(int, nr_pins);
apic_pin_2_ir_idx = xmalloc_array(int *, nr_ioapics);
for ( i = 0; i < nr_ioapics; i++ )
{
apic_pin_2_ir_idx[i] = &_apic_pin_2_ir_idx[nr_pins];
- nr_pins += nr_ioapic_registers(i);
+ nr_pins += nr_ioapic_entries(i);
}
return 0;