mov %eax,sym_phys(boot_tsc_stamp)
mov %edx,sym_phys(boot_tsc_stamp+4)
- /* Initialise L2 boot-map page table entries (16MB). */
- mov $sym_phys(l2_bootmap),%edx
- mov $PAGE_HYPERVISOR|_PAGE_PSE,%eax
- mov $8,%ecx
-1: mov %eax,(%edx)
- add $8,%edx
- add $(1<<L2_PAGETABLE_SHIFT),%eax
- loop 1b
- /* Initialise L3 boot-map page directory entry. */
- mov $sym_phys(l2_bootmap)+__PAGE_HYPERVISOR,%eax
- mov %eax,sym_phys(l3_bootmap) + 0*8
- /* Hook 4kB mappings of first 2MB of memory into L2. */
+ /*
+ * During boot, hook 4kB mappings of first 2MB of memory into L2.
+ * This avoids mixing cachability for the legacy VGA region, and is
+ * corrected when Xen relocates itself.
+ */
mov $sym_phys(l1_identmap)+__PAGE_HYPERVISOR,%edi
mov %edi,sym_phys(l2_xenmap)
- mov %edi,sym_phys(l2_bootmap)
/* Apply relocations to bootstrap trampoline. */
mov sym_phys(trampoline_phys),%edx
.size idle_pg_table, . - idle_pg_table
GLOBAL(__page_tables_end)
+
+/* Init pagetables. Enough page directories to map into the bottom 1GB. */
+ .section .init.data, "a", @progbits
+ .align PAGE_SIZE, 0
+
+GLOBAL(l2_bootmap)
+ .quad sym_phys(l1_identmap) + __PAGE_HYPERVISOR
+ idx = 1
+ .rept 7
+ .quad (idx << L2_PAGETABLE_SHIFT) | __PAGE_HYPERVISOR | _PAGE_PSE
+ idx = idx + 1
+ .endr
+ .fill L2_PAGETABLE_ENTRIES - 8, 8, 0
+ .size l2_bootmap, . - l2_bootmap
+
+GLOBAL(l3_bootmap)
+ .quad sym_phys(l2_bootmap) + __PAGE_HYPERVISOR
+ .fill L3_PAGETABLE_ENTRIES - 1, 8, 0
+ .size l3_bootmap, . - l3_bootmap
unsigned int __read_mostly m2p_compat_vstart = __HYPERVISOR_COMPAT_VIRT_START;
-/* Enough page directories to map into the bottom 1GB. */
-l3_pgentry_t __section(".bss.page_aligned") l3_bootmap[L3_PAGETABLE_ENTRIES];
-l2_pgentry_t __section(".bss.page_aligned") l2_bootmap[L2_PAGETABLE_ENTRIES];
-
l2_pgentry_t *compat_idle_pg_table_l2;
void *do_page_walk(struct vcpu *v, unsigned long addr)