x86/cpu: add support for zhaoxin x86 platform

Zhaoxin is a x86 IC designer. Its SOC products support both CPU
virtualization and I/O virtualization, which are compatible with Intel
VMX and VT-d respectively. Zhaoxin has 'Shanghai' CPU vendor ID.

Signed-off-by: DavidWang <davidwang@zhaoxin.com>
Acked-by: Jan Beulich <jbeulich@suse.com>

diff --git a/xen/arch/x86/cpu/Makefile b/xen/arch/x86/cpu/Makefile
index 74f23aee0fd58a9d562c7daabc1ed9b9d1e766b5..34a01ca061c4a89ee107d58bdc6c98f902bdc0dd 100644 (file)
--- a/xen/arch/x86/cpu/Makefile
+++ b/xen/arch/x86/cpu/Makefile
@@ -7,4 +7,5 @@ obj-y += common.o
 obj-y += intel.o
 obj-y += intel_cacheinfo.o
 obj-y += mwait-idle.o
+obj-y += shanghai.o
 obj-y += vpmu.o vpmu_amd.o vpmu_intel.o

diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index bdd45c30fb952e31b1edf35411a3bb5e67ed0578..e6a592256f65b2a1d05e814b8d2abad4a8c16983 100644 (file)
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -700,6 +700,7 @@ void __init early_cpu_init(void)
        intel_cpu_init();
        amd_init_cpu();
        centaur_init_cpu();
+       shanghai_init_cpu();
        early_cpu_detect();
 }
 

diff --git a/xen/arch/x86/cpu/cpu.h b/xen/arch/x86/cpu/cpu.h
index 4ac2034c698ff4707b3a08fa8ac1c8804173e708..2fcb93138829f05ebe2edb923376c3be99a3b4da 100644 (file)
--- a/xen/arch/x86/cpu/cpu.h
+++ b/xen/arch/x86/cpu/cpu.h
@@ -20,3 +20,4 @@ extern void display_cacheinfo(struct cpuinfo_x86 *c);
 int intel_cpu_init(void);
 int amd_init_cpu(void);
 int centaur_init_cpu(void);
+int shanghai_init_cpu(void);

diff --git a/xen/arch/x86/cpu/intel_cacheinfo.c b/xen/arch/x86/cpu/intel_cacheinfo.c
index 4ffcf1b6a079288ead2af3cf1b65124be493bca7..88b61fddfe230619514bb5e85cffed07e6130665 100644 (file)
--- a/xen/arch/x86/cpu/intel_cacheinfo.c
+++ b/xen/arch/x86/cpu/intel_cacheinfo.c
@@ -168,7 +168,9 @@ unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
         * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
         * trace cache
         */
-       if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
+       if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1 &&
+           c->x86_vendor != X86_VENDOR_SHANGHAI)
+       {
                /* supports eax=2  call */
                int i, j, n;
                int regs[4];

diff --git a/xen/arch/x86/cpu/shanghai.c b/xen/arch/x86/cpu/shanghai.c
new file mode 100644 (file)
index 0000000..9156c85
--- /dev/null
+++ b/xen/arch/x86/cpu/shanghai.c
@@ -0,0 +1,28 @@
+#include <xen/bitops.h>
+#include <xen/init.h>
+#include <asm/processor.h>
+#include "cpu.h"
+
+static void init_shanghai(struct cpuinfo_x86 *c)
+{
+    if ( cpu_has(c, X86_FEATURE_ITSC) )
+    {
+        __set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
+        __set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability);
+        __set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability);
+    }
+
+    init_intel_cacheinfo(c);
+}
+
+static const struct cpu_dev shanghai_cpu_dev = {
+    .c_vendor   = "  Shang",
+    .c_ident    = {"  Shanghai  "},
+    .c_init     = init_shanghai,
+};
+
+int __init shanghai_init_cpu(void)
+{
+    cpu_devs[X86_VENDOR_SHANGHAI] = &shanghai_cpu_dev;
+    return 0;
+}

diff --git a/xen/include/asm-x86/x86-vendors.h b/xen/include/asm-x86/x86-vendors.h
index cae5507bd08829dd70ecc163b81a9fdd3a154646..c53d0b9bafb21ae6722882a719c6d6487f1e8b5f 100644 (file)
--- a/xen/include/asm-x86/x86-vendors.h
+++ b/xen/include/asm-x86/x86-vendors.h
@@ -7,7 +7,8 @@
 #define X86_VENDOR_INTEL 0
 #define X86_VENDOR_AMD 1
 #define X86_VENDOR_CENTAUR 2
-#define X86_VENDOR_NUM 3
+#define X86_VENDOR_SHANGHAI 3
+#define X86_VENDOR_NUM 4
 #define X86_VENDOR_UNKNOWN 0xff
 
 #endif /* __XEN_X86_VENDORS_H__ */