]> xenbits.xensource.com Git - people/royger/xen.git/commitdiff
x86/vm_event: add gdtr_base to the vm_event structure
authorTamas K Lengyel <tamas@tklengyel.com>
Mon, 13 May 2019 07:56:41 +0000 (09:56 +0200)
committerJan Beulich <jbeulich@suse.com>
Mon, 13 May 2019 07:56:41 +0000 (09:56 +0200)
Receiving this register is useful for introspecting 32-bit Windows when the
event being trapped happened while in ring3.

Signed-off-by: Tamas K Lengyel <tamas@tklengyel.com>
Acked-by: Razvan Cojocaru <rcojocaru@bitdefender.com>
xen/arch/x86/vm_event.c
xen/include/public/vm_event.h

index 51c3493b1d765be86847712939a494f9b6306ed0..52c2a71fa0ad21574be2a26768b877c98e055303 100644 (file)
@@ -179,6 +179,11 @@ static void vm_event_pack_segment_register(enum x86_segment segment,
         reg->es_sel = seg.sel;
         break;
 
+    case x86_seg_gdtr:
+        reg->gdtr_base = seg.base;
+        reg->gdtr_limit = seg.limit;
+        break;
+
     default:
         ASSERT_UNREACHABLE();
     }
@@ -238,6 +243,7 @@ void vm_event_fill_regs(vm_event_request_t *req)
     vm_event_pack_segment_register(x86_seg_ss, &req->data.regs.x86);
     vm_event_pack_segment_register(x86_seg_ds, &req->data.regs.x86);
     vm_event_pack_segment_register(x86_seg_es, &req->data.regs.x86);
+    vm_event_pack_segment_register(x86_seg_gdtr, &req->data.regs.x86);
 
     req->data.regs.x86.shadow_gs = ctxt.shadow_gs;
     req->data.regs.x86.dr6 = ctxt.dr6;
index b2bafc0d77f9758e42b0d53c05a7e6bb86c86686..959083d8c47a3f8742d709267f2c1c869eed5858 100644 (file)
@@ -29,7 +29,7 @@
 
 #include "xen.h"
 
-#define VM_EVENT_INTERFACE_VERSION 0x00000004
+#define VM_EVENT_INTERFACE_VERSION 0x00000005
 
 #if defined(__XEN__) || defined(__XEN_TOOLS__)
 
@@ -198,6 +198,7 @@ struct vm_event_regs_x86 {
     uint64_t msr_efer;
     uint64_t msr_star;
     uint64_t msr_lstar;
+    uint64_t gdtr_base;
     uint32_t cs_base;
     uint32_t ss_base;
     uint32_t ds_base;
@@ -211,13 +212,14 @@ struct vm_event_regs_x86 {
     struct vm_event_x86_selector_reg fs;
     struct vm_event_x86_selector_reg gs;
     uint64_t shadow_gs;
+    uint16_t gdtr_limit;
     uint16_t cs_sel;
     uint16_t ss_sel;
     uint16_t ds_sel;
     uint16_t es_sel;
     uint16_t fs_sel;
     uint16_t gs_sel;
-    uint32_t _pad;
+    uint16_t _pad;
 };
 
 /*