]> xenbits.xensource.com Git - qemu-xen.git/commitdiff
hw/arm/virt-acpi-build: Fix GSIV values of the {GERR, Sync} interrupts
authorZenghui Yu <yuzenghui@huawei.com>
Fri, 2 Apr 2021 08:47:31 +0000 (16:47 +0800)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 12 Apr 2021 10:06:24 +0000 (11:06 +0100)
The GSIV values in SMMUv3 IORT node are not correct as they don't match
the SMMUIrq enumeration, which describes the IRQ<->PIN mapping used by
our emulated vSMMU.

Fixes: a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Acked-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20210402084731.93-1-yuzenghui@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm/virt-acpi-build.c

index f5a2b2d4cb569f0c71bd14b91f37ff15406cfd57..60fe2e65a76101ac21408e1edbeeeafa40fa0520 100644 (file)
@@ -292,8 +292,8 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
         smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
         smmu->event_gsiv = cpu_to_le32(irq);
         smmu->pri_gsiv = cpu_to_le32(irq + 1);
-        smmu->gerr_gsiv = cpu_to_le32(irq + 2);
-        smmu->sync_gsiv = cpu_to_le32(irq + 3);
+        smmu->sync_gsiv = cpu_to_le32(irq + 2);
+        smmu->gerr_gsiv = cpu_to_le32(irq + 3);
 
         /* Identity RID mapping covering the whole input RID range */
         idmap = &smmu->id_mapping_array[0];