xen/arch/x86/cpu/intel.c: Report SMX and TXT capabilities

Report the SMX and TXT capabilitiesso that dom0 can query the
Intel TXT support information using xl dmesg.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>

diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c
index 2d439e0bd2fd54d4ca6c4b52554fccde46610b0a..f11eb8d3722f8984306c972e9d88550b4b6c45b7 100644 (file)
--- a/xen/arch/x86/cpu/intel.c
+++ b/xen/arch/x86/cpu/intel.c
@@ -13,6 +13,7 @@
 #include <asm/i387.h>
 #include <mach_apic.h>
 #include <asm/hvm/support.h>
+#include <asm/intel_txt.h>
 
 #include "cpu.h"
 
@@ -525,6 +526,47 @@ static void intel_log_freq(const struct cpuinfo_x86 *c)
     printk("%u MHz\n", (factor * max_ratio + 50) / 100);
 }
 
+/*
+ * Print out the SMX and TXT capabilties, so that dom0 can determine if system
+ * is DRTM capable
+ */
+static void intel_log_smx_txt(struct cpuinfo_x86 *c)
+{
+       unsigned long cr4_val, getsec_caps;
+       
+       /* Run only on BSP to report the SMX/TXT caps only once */
+       if (smp_processor_id())
+               return;
+
+       printk("CPU: SMX capability ");
+       if (!test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability)) {
+               printk("not supported\n");
+               return;
+       }
+       printk("supported\n");
+
+       /* Can't run GETSEC without VMX and SMX */
+       if (!test_bit(X86_FEATURE_VMX, &boot_cpu_data.x86_capability))
+               return;
+
+       cr4_val = read_cr4();
+       if (!(cr4_val & X86_CR4_SMXE))
+               write_cr4(cr4_val | X86_CR4_SMXE);
+
+       asm volatile ("getsec\n"
+               : "=a" (getsec_caps)
+               : "a" (GETSEC_CAPABILITIES), "b" (0) :);
+       
+       if (getsec_caps & GETSEC_CAP_TXT_CHIPSET)
+               printk("Chipset supports TXT\n");
+       else
+               printk("Chipset does not support TXT\n");
+
+       if (!(cr4_val & X86_CR4_SMXE))
+               write_cr4(cr4_val & ~X86_CR4_SMXE);
+
+}
+
 static void cf_check init_intel(struct cpuinfo_x86 *c)
 {
        /* Detect the extended topology information if available */
@@ -565,6 +607,8 @@ static void cf_check init_intel(struct cpuinfo_x86 *c)
                detect_ht(c);
        }
 
+       intel_log_smx_txt(c);
+
        /* Work around errata */
        Intel_errata_workarounds(c);
 

diff --git a/xen/arch/x86/include/asm/intel_txt.h b/xen/arch/x86/include/asm/intel_txt.h
index 93b7707a36fa943667fcdcc280c047ae3e2d5712..5d171d4e9f262d4730ed04f6811a4c03bae7069b 100644 (file)
--- a/xen/arch/x86/include/asm/intel_txt.h
+++ b/xen/arch/x86/include/asm/intel_txt.h
@@ -76,6 +76,11 @@
 #define TXT_AP_BOOT_CS                  0x0030
 #define TXT_AP_BOOT_DS                  0x0038
 
+/* EAX value for GETSEC leaf functions. Intel SDM: GETSEC[CAPABILITIES] */
+#define GETSEC_CAPABILITIES             0
+/* Intel SDM: GETSEC Capability Result Encoding */
+#define GETSEC_CAP_TXT_CHIPSET          1
+
 #ifndef __ASSEMBLY__
 
 extern char txt_ap_entry[];