HACK: Enable evtchn and timer IRQ on secondary CPUs

diff --git a/sys/arm/arm/gic.c b/sys/arm/arm/gic.c
index 607e02ad2cdd953f37f7f3c3bcd82f507af35748..7e5e08317b6f3d46a200351770b40e1c5b7d11a0 100644 (file)
--- a/sys/arm/arm/gic.c
+++ b/sys/arm/arm/gic.c
@@ -194,6 +194,8 @@ gic_init_secondary(device_t dev)
        gic_d_write_4(sc, GICD_ISENABLER(27 >> 5), (1UL << (27 & 0x1F)));
        gic_d_write_4(sc, GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
        gic_d_write_4(sc, GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F)));
+       /* Activate IRQ 31, ie private evtchn IRQ */
+       gic_d_write_4(sc, GICD_ISENABLER(31 >> 5), (1UL << (31 & 0x1F)));
 }
 
 #if 0