Both Cortex-A57 (erratum
1319537) and Cortex-A72 (erratum
1319367) can
end with corrupted TLBs if they speculate an AT instruction while S1/S2
system registers in inconsistent state.
The workaround is the same as for Cortex A-76 implemented by commit
a18be06aca "xen/arm: Implement workaround for Cortex-A76 erratum
1165522",
so it is only necessary to plumb in the cpuerrata framework.
Signed-off-by: Julien Grall <julien.grall@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>
| ARM | Cortex-A57 | #852523 | N/A |
| ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
+| ARM | Cortex-A57 | #1319537 | N/A |
+| ARM | Cortex-A72 | #1319367 | N/A |
| ARM | Cortex-A76 | #1165522 | N/A |
| ARM | MMU-500 | #842869 | N/A |
.capability = ARM64_WORKAROUND_AT_SPECULATE,
MIDR_RANGE(MIDR_CORTEX_A76, 0, 2 << MIDR_VARIANT_SHIFT),
},
+ {
+ .desc = "ARM erratum 1319537",
+ .capability = ARM64_WORKAROUND_AT_SPECULATE,
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
+ },
+ {
+ .desc = "ARM erratum 1319367",
+ .capability = ARM64_WORKAROUND_AT_SPECULATE,
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
+ },
{},
};