ivrs_mappings[alias_id].intremap_table = shared_intremap_table;
ivrs_mappings[alias_id].intremap_inuse = shared_intremap_inuse;
}
+
+ if ( !ivrs_mappings[alias_id].intremap_table )
+ panic("No memory for %04x:%02x:%02x.%u's IRT\n", iommu->seg,
+ PCI_BUS(alias_id), PCI_SLOT(alias_id), PCI_FUNC(alias_id));
}
ivrs_mappings[alias_id].valid = true;
void *__init amd_iommu_alloc_intremap_table(
const struct amd_iommu *iommu, unsigned long **inuse_map)
{
- void *tb = __alloc_amd_iommu_tables(intremap_table_order(iommu));
+ unsigned int order = intremap_table_order(iommu);
+ void *tb = __alloc_amd_iommu_tables(order);
+
+ if ( tb )
+ {
+ *inuse_map = xzalloc_array(unsigned long,
+ BITS_TO_LONGS(INTREMAP_ENTRIES));
+ if ( *inuse_map )
+ memset(tb, 0, PAGE_SIZE << order);
+ else
+ {
+ __free_amd_iommu_tables(tb, order);
+ tb = NULL;
+ }
+ }
- BUG_ON(tb == NULL);
- memset(tb, 0, PAGE_SIZE << intremap_table_order(iommu));
- *inuse_map = xzalloc_array(unsigned long, BITS_TO_LONGS(INTREMAP_ENTRIES));
- BUG_ON(*inuse_map == NULL);
return tb;
}