x86: avoid needless EPT table ajustment and cache flush

When a guest change it's MTRR MSRs, ajusting EPT table and flushing
cache are needed only when guest has IOMMU device, using need_iommu(d)
can minimize the impact to guest with device assigned, since a guest
may be hot plugged with a device thus there may be dirty cache lines
before need_iommu(d) becoming true, force the p2m_memory_type_changed
and flush_all when the first device is assigned to guest to amend this
issue.

Signed-off-by: Liang Li <liang.z.li@intel.com>
Signed-off-by: Yang Zhang <yang.z.zhang@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

diff --git a/xen/arch/x86/hvm/mtrr.c b/xen/arch/x86/hvm/mtrr.c
index 76b3c2a6601adeee36a57cbcf1903524dc8f6153..a69ee62a654675c6ce3308f7d151854eafd339b7 100644 (file)
--- a/xen/arch/x86/hvm/mtrr.c
+++ b/xen/arch/x86/hvm/mtrr.c
@@ -789,7 +789,7 @@ HVM_REGISTER_SAVE_RESTORE(MTRR, hvm_save_mtrr_msr, hvm_load_mtrr_msr,
 
 void memory_type_changed(struct domain *d)
 {
-    if ( iommu_enabled && d->vcpu && d->vcpu[0] )
+    if ( need_iommu(d) && d->vcpu && d->vcpu[0] )
     {
         p2m_memory_type_changed(d);
         flush_all(FLUSH_CACHE);

diff --git a/xen/drivers/passthrough/pci.c b/xen/drivers/passthrough/pci.c
index 78c6977d74823443367de11ea412b0b97e3d4bce..b93e7d8e718eb76f2b39c6d741c44f9b452cde93 100644 (file)
--- a/xen/drivers/passthrough/pci.c
+++ b/xen/drivers/passthrough/pci.c
@@ -1365,6 +1365,13 @@ static int assign_device(struct domain *d, u16 seg, u8 bus, u8 devfn)
             }
         }
         d->need_iommu = 1;
+        /*
+         * There may be dirty cache lines when a device is assigned
+         * and before need_iommu(d) becoming true, this will cause
+         * memory_type_changed lose effect if memory type changes.
+         * Call memory_type_changed here to amend this.
+         */
+        memory_type_changed(d);
     }
 
     pdev = pci_get_pdev_by_domain(hardware_domain, seg, bus, devfn);