arm/acpi: Add Server Base System Architecture UART support

The ARM Server Base System Architecture describes a generic UART
interface. It doesn't support clock control registers, modem
control, DMA and hardware flow control features. So, extend the
driver probe() to handle SBSA interface and skip the accessing
PL011 registers that are not described in SBSA document
(ARM-DEN-0029 Version 3.0, 6 APPENDIX B: GENERIC UART).

Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Signed-off-by: Stefano Stabellini <sstabellini@kernel.org>

diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c
index 664dda6d137054600c653d9ec2bda356d0e4e099..102f40d557918b801476f883dcf80270e5a409e2 100644 (file)
--- a/xen/drivers/char/pl011.c
+++ b/xen/drivers/char/pl011.c
@@ -41,6 +41,7 @@ static struct pl011 {
     /* struct timer timer; */
     /* unsigned int timeout_ms; */
     /* bool_t probing, intr_works; */
+    bool sbsa;  /* ARM SBSA generic interface */
 } pl011_com = {0};
 
 /* These parity settings can be ORed directly into the LCR. */
@@ -50,6 +51,7 @@ static struct pl011 {
 #define PARITY_MARK  (PEN|SPS)
 #define PARITY_SPACE (PEN|EPS|SPS)
 
+/* SBSA v2.x document requires, all reads/writes must be 32-bit accesses */
 #define pl011_read(uart, off)           readl((uart)->regs + (off))
 #define pl011_write(uart, off,val)      writel((val), (uart)->regs + (off))
 
@@ -95,14 +97,17 @@ static void __init pl011_init_preirq(struct serial_port *port)
     /* No interrupts, please. */
     pl011_write(uart, IMSC, 0);
 
-    /* Definitely no DMA */
-    pl011_write(uart, DMACR, 0x0);
-
-    /* This write must follow FBRD and IBRD writes. */
-    pl011_write(uart, LCR_H, (uart->data_bits - 5) << 5
-                            | FEN
-                            | ((uart->stop_bits - 1) << 3)
-                            | uart->parity);
+    if ( !uart->sbsa )
+    {
+        /* Definitely no DMA */
+        pl011_write(uart, DMACR, 0x0);
+
+        /* This write must follow FBRD and IBRD writes. */
+        pl011_write(uart, LCR_H, (uart->data_bits - 5) << 5
+                                | FEN
+                                | ((uart->stop_bits - 1) << 3)
+                                | uart->parity);
+    }
     /* Clear errors */
     pl011_write(uart, RSR, 0);
 
@@ -110,10 +115,13 @@ static void __init pl011_init_preirq(struct serial_port *port)
     pl011_write(uart, IMSC, 0);
     pl011_write(uart, ICR, ALLI);
 
-    /* Enable the UART for RX and TX; keep RTS and DTR */
-    cr = pl011_read(uart, CR);
-    cr &= RTS | DTR;
-    pl011_write(uart, CR, cr | RXE | TXE | UARTEN);
+    if ( !uart->sbsa )
+    {
+        /* Enable the UART for RX and TX; keep RTS and DTR */
+        cr = pl011_read(uart, CR);
+        cr &= RTS | DTR;
+        pl011_write(uart, CR, cr | RXE | TXE | UARTEN);
+    }
 }
 
 static void __init pl011_init_postirq(struct serial_port *port)
@@ -215,7 +223,7 @@ static struct uart_driver __read_mostly pl011_driver = {
     .vuart_info   = pl011_vuart,
 };
 
-static int __init pl011_uart_init(int irq, u64 addr, u64 size)
+static int __init pl011_uart_init(int irq, u64 addr, u64 size, bool sbsa)
 {
     struct pl011 *uart;
 
@@ -224,6 +232,7 @@ static int __init pl011_uart_init(int irq, u64 addr, u64 size)
     uart->data_bits = 8;
     uart->parity    = PARITY_NONE;
     uart->stop_bits = 1;
+    uart->sbsa      = sbsa;
 
     uart->regs = ioremap_nocache(addr, size);
     if ( !uart->regs )
@@ -272,7 +281,7 @@ static int __init pl011_dt_uart_init(struct dt_device_node *dev,
         return -EINVAL;
     }
 
-    res = pl011_uart_init(res, addr, size);
+    res = pl011_uart_init(res, addr, size, false);
     if ( res < 0 )
     {
         printk("pl011: Unable to initialize\n");
@@ -303,6 +312,7 @@ static int __init pl011_acpi_uart_init(const void *data)
     acpi_status status;
     struct acpi_table_spcr *spcr = NULL;
     int res;
+    bool sbsa;
 
     status = acpi_get_table(ACPI_SIG_SPCR, 0,
                             (struct acpi_table_header **)&spcr);
@@ -313,11 +323,14 @@ static int __init pl011_acpi_uart_init(const void *data)
         return -EINVAL;
     }
 
+    sbsa = (spcr->interface_type == ACPI_DBG2_SBSA ||
+            spcr->interface_type == ACPI_DBG2_SBSA_32);
+
     /* trigger/polarity information is not available in spcr */
     irq_set_type(spcr->interrupt, IRQ_TYPE_LEVEL_HIGH);
 
     res = pl011_uart_init(spcr->interrupt, spcr->serial_port.address,
-                          PAGE_SIZE);
+                          PAGE_SIZE, sbsa);
     if ( res < 0 )
     {
         printk("pl011: Unable to initialize\n");
@@ -331,6 +344,17 @@ ACPI_DEVICE_START(apl011, "PL011 UART", DEVICE_SERIAL)
         .class_type = ACPI_DBG2_PL011,
         .init = pl011_acpi_uart_init,
 ACPI_DEVICE_END
+
+ACPI_DEVICE_START(asbsa_uart, "SBSA UART", DEVICE_SERIAL)
+    .class_type = ACPI_DBG2_SBSA,
+    .init = pl011_acpi_uart_init,
+ACPI_DEVICE_END
+
+ACPI_DEVICE_START(asbsa32_uart, "SBSA32 UART", DEVICE_SERIAL)
+    .class_type = ACPI_DBG2_SBSA_32,
+    .init = pl011_acpi_uart_init,
+ACPI_DEVICE_END
+
 #endif
 
 /*