#define BUILD_APIC_ADDR 0xfee00000
// PCI IRQS
-#define BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
+#define BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
// Important real-mode segments
#define SEG_IVT 0x0000
switch (acpi_reset_reg.address_space_id) {
case 0: // System Memory
- writeb((void *)(u32)addr, acpi_reset_val);
+ writeb((void *)(u32)addr, acpi_reset_val);
break;
case 1: // System I/O
outb(acpi_reset_val, addr);
#define CB_TAG_CBMEM_CONSOLE 0x17
struct cbmem_console {
- u32 buffer_size;
- u32 buffer_cursor;
- u8 buffer_body[0];
+ u32 buffer_size;
+ u32 buffer_cursor;
+ u8 buffer_body[0];
} PACKED;
static struct cbmem_console *cbcon = NULL;
smm_device_setup(void)
{
if (!CONFIG_USE_SMM)
- return;
+ return;
struct pci_device *isapci, *pmpci;
isapci = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3);
smm_setup(void)
{
if (!CONFIG_USE_SMM || SMMISADeviceBDF < 0)
- return;
+ return;
dprintf(3, "init smm\n");
u16 device = pci_config_readw(SMMISADeviceBDF, PCI_DEVICE_ID);
}
}
- /* At end of DMA TC is set again -> complete command. */
+ /* At end of DMA TC is set again -> complete command. */
if (state == 1 && (stat & ESP_STAT_TC)) {
state++;
outb(ESP_CMD_ICCS, iobase + ESP_CMD);
continue;
}
- /* Finally read data from the message in phase. */
+ /* Finally read data from the message in phase. */
if (state == 2 && (stat & ESP_STAT_MSG)) {
state++;
status = inb(iobase + ESP_FIFO);
#define MSR_GLIU0 (1 << 28)
#define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* LX */
#define GLIU0_P2D_BM_4 (MSR_GLIU0 + 0x24) /* GX2 */
-#define GLIU0_P2D_RO (MSR_GLIU0 + 0x29)
+#define GLIU0_P2D_RO (MSR_GLIU0 + 0x29)
#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0)
#define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1)
#define DC_SPARE 0x80000011