#define ASPEED_SOC_SCU_BASE 0x1E6E2000
#define ASPEED_SOC_SRAM_BASE 0x1E720000
#define ASPEED_SOC_TIMER_BASE 0x1E782000
+#define ASPEED_SOC_WDT_BASE 0x1E785000
#define ASPEED_SOC_I2C_BASE 0x1E78A000
static const int uart_irqs[] = { 9, 32, 33, 34, 10 };
sc->info->silicon_rev);
object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
"ram-size", &error_abort);
+
+ object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ASPEED_WDT);
+ object_property_add_child(obj, "wdt", OBJECT(&s->wdt), NULL);
+ qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default());
}
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdmc), 0, ASPEED_SOC_SDMC_BASE);
+
+ /* Watch dog */
+ object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt), 0, ASPEED_SOC_WDT_BASE);
}
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
#include "hw/timer/aspeed_timer.h"
#include "hw/i2c/aspeed_i2c.h"
#include "hw/ssi/aspeed_smc.h"
+#include "hw/watchdog/wdt_aspeed.h"
#define ASPEED_SPIS_NUM 2
AspeedSMCState fmc;
AspeedSMCState spi[ASPEED_SPIS_NUM];
AspeedSDMCState sdmc;
+ AspeedWDTState wdt;
} AspeedSoCState;
#define TYPE_ASPEED_SOC "aspeed-soc"